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μ
PD17016, 17017
196
Table 15-3. Software Macros Setting Ports (P0E and P0F)
Function
Macro Format
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
pins as general-purpose output port
SET1_P0EON
Uses LCD
26
/P0F
0
-LCD
29
/P0F
3
pins as general-purpose output port
SET1_P0FON
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
pins and LCD
26
/P0F
0
-LCD
29
/P0F
3
pins as general-purpose
output port
SET2_P0EON_P0FON
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
pins as LCD segment signal output pins
CLR1_P0EON
Uses LCD
26
/P0F
0
-LCD
29
/P0F
3
pins as LCD segment signal output pins
CLR1_P0FON
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
and LCD
26
/P0F
0
-LCD
29
/P0F
3
pins as LCD segment signal
output pins
CLR2_P0EON_P0FON
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
pins as LCD segment signal output pins and LCD
26
/ P0F
0
-
LCD
29
/P0F
3
pins as general-purpose output port
INIT_NOT_P0EON_P0FON
Uses LCD
22
/P0E
0
-LCD
25
/P0E
3
pins as general-purpose output port and LCD
26
/P0F
0
-LCD
29
/
P0F
3
pins as LCD segment signal output pins
INIT_P0EON_NOT_P0FON
Caution
If the above macros are used, the contents of the window register are destroyed.
If the above macros are immediately follow an embedded macro instruction, an “object error”
occurs when the source file is assembled and loaded to the in-circuit emulator. If an embedded
macro is used before the above macros, insert a comment statement in between them.
15.6.3 Setting data to P0E and P0F
Output data are set to the P0E and P0F by executing an instruction, such as “MOV”, that writes data to the
port registers corresponding to the ports.
To output a high level to each port pin, write “1” to the corresponding port register; to output a low level, write
“0”.
The contents of the output latch are read when an instruction, such as “SKT”, that reads the contents of the
port register is executed.
Figure 15-3 shows the relation between the P0F port register and LCD segment register.
As shown in this figure, LCD segment register LCDD14 can be used as a general-purpose data memory area
when the P0F is used.
The same applies to the P0E.
Refer to
Figure 21-6. Relation among LCD Display Dots, Ports 0E and 0F, Key Source Output, and Each
Data Setting Register
in
21. LCD CONTROLLER/DRIVER
.
Figure 15-3. Relation between P0F Port Register and LCD Segment Register
P0FON flag
LCD
29
/P0F
3
1
0
Segment signal
timing control
LCDD14
(6EH)
b
3
b
2
LCD
28
/P0F
2
1
0
Segment signal
timing control
b
1
b
0
LCD
27
/P0F
1
1
0
Segment signal
timing control
b
3
b
2
LCD
26
/P0F
0
1
0
Segment signal
timing control
b
1
b
0
LCDD13
P0F
(6DH)