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μ
PD17016, 17017
190
15.3.6 Notes on using I/O ports (P0A
3
and P0A
2
pins)
When using the P0A
3
and P0A
2
pins as output pins, the contents of the output latch may be rewritten, as shown
in the example below.
Example To specify P0A
3
and P0A
2
pins as output port pins
INITFLG P0ABI03, P0ABI02, NOT P0ABI01, NOT P0ABI00
; Sets P0A
3
and P0A
2
pins in output mode
INITFLG P0A3, P0A2, NOT P0A1, NOT P0A0
; Outputs high level to P0A
3
and P0A
2
pins
;<1>
CLR1
P0A3
; Outputs low level to P0A
3
pin
Macro expansion
AND
. MF. P0A3 SHR 4, # .DF. (NOT P0A3 AND 0FH)
If the P0A
2
pin happens to be lowered by an external device when the instruction in <1> above is executed,
the contents of the output latch of the P0A
2
pin are rewritten to “0” by the “CLR1” instruction.
In other words, if an operation instruction (such as “ADD” and “OR”) to the P0A port register when the P0A
3
or P0A
2
pin is set in the output mode, the contents of the output latch are rewritten to the current level of the
pin, regardless of the previous status of the pin.
15.3.7 Status of I/O ports (P0A, P0B, P0C, and P1A) on reset
(1) On power-ON reset
All the I/O ports are set in the input mode.
Because the contents of the output latch are “undefined”, the output latch must be initialized by program, as
necessary, before setting the corresponding port in the output mode.
(2) On CE reset
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
(3) On execution of clock stop instruction
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
The I/O ports other than P0C prevents an increase in the current dissipation due to the noise of the input buffer
by using the RESET signal when the clock stop instruction is executed, as explained in 15.3.1.
If P0C is floated on execution of the clock stop instruction, the current dissipation may increase due to external
noise. Externally pull this port down or up as necessary.
(4) In halt status
The previous status is retained.