
1999 May 10
24
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
MEMORY AND REGISTER SPACE 80C51
Overview registers
Table 15
Register location and recommended values
after Power-on reset
Table 16
Special function register location
ADDRESS
REGISTER
RESET
VALUE
0800h
0801h
1000h
1001h
1002h
1003h
2000h
4000h
4001h
PGA gain
ADIF control
clock shop settings
reset control and APLL settings
IO selection register
power control
ASR settings
data register PSIE
command register PSIE
09
5C
00
00
01
00
8B
ADDRESS
REGISTER
RESET
VALUE
CPU registers
81h
82h
83h
D0h
E0h
F0h
SP
DPL
DPH
PSW
ACC
B
Interrupt registers
A8h
B8h
IE
IP
00h
00h
Timer 0 and Timer 1 registers
88h
89h
8Ah
8Bh
8Ch
8Dh
T01CON
T01MOD
T0L
T1L
T0h
T1h
00h
00h
00h
00h
00h
00h
PCON registers
87h
PCON
00h
Interrupts
The UDA1325 supports up to five (of maximal 7) interrupt
sources. Each interrupt source corresponds to an interrupt
vector in the CPU program memory address space:
Source 0: vector 0003h external interrupt 0 (INT0_N)
Source 1: vector 000Bh Timer 0 interrupt
Source 2: vector 0013h external interrupt 1 (INT1_N)
Source 3: vector 001Bh Timer 1 interrupt
Source 4: vector 0023h UART interrupt (not present)
Source 5: vector 002Bh Timer 2 interrupt (not present)
Source 6: vector 0033h I
2
C interrupt.
I
NTERRUPT
E
NABLE REGISTER
(IE)
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in IE. This register also
contains a global interrupt enable bit (EA) which can be
cleared to disable all interrupts at once.
Port registers
80h
90h
A0h
B0h
P0
P1
P2
P3
FFh
FFh
FFh
FFh
I
2
C registers (SIO1 registers)
D8h
D9h
DAh
DBh
S1CON
S1STA
S1DAT
S1ADR
00h
ADDRESS
REGISTER
RESET
VALUE
0
0
0
0
0
0
0
0
EX0 (vector 0003h))
ET0 (vector 000Bh))
EX1 (vector 0013h)
ET1 (vector 001Bh)
ES0 (n.a.)
ET2 (n.a.)
ES1 (vector 0033h)
EA
7
6
5
4
3
2
1
0
Power On Value