參數(shù)資料
型號(hào)： UDA1325
廠商： NXP Semiconductors N.V.
元件分類(lèi)： Codec
英文描述： Universal Serial Bus USB CODEC
中文描述： 通用串行總線解碼器
文件頁(yè)數(shù)： 11/52頁(yè)
文件大?。?/td> 310K
代理商： UDA1325
1999 May 10
11
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
The clock source of the analog-to-digital interface
The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected.
The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog
PLL or from the ADC oscillator by a factor Q.
Using the analog PLL the user can select 3 basic APLL clock frequencies (see Table 1).
By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC
oscillator.
Table 1
The analog PLL clock output frequencies
The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of
ADC clock signals allowing several different sample frequencies (see Table 2).
Table 2
ADC clock frequencies and sample frequencies based upon using the APLL as a clock source
Table 3
ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source
Notes
1.
2.
3.
The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz.
The Q factor can be 1, 2, 4 or 8.
Sample frequencies below 5 kHz and above 55 kHz are not supported.
FCODE (1 AND 0)
APLL CLOCK
FREQUENCY (MHz)
00
01
10
11
11.2896
8.1920
12.2880
11.2896
APLL CLOCK
FREQUENCY (MHz)
8.1920
DIVIDE FACTOR Q
ADC CLOCK FREQUENCY (MHz)
SAMPLE FREQUENCY (kHz)
1
2
4
8
1
2
4
8
1
2
4
8
4.096
2.048
1.024
32
16
8
0.512 (not supported)
5.6448
2.8224
1.4112
0.7056
6.144
3.072
1.536
0.768
4 (not supported)
44.1
22.05
11.025
5.5125
48
24
12
6
11.2896
12.2880
OSCAD CLOCK
FREQUENCY (MHz)
f
osc(1)
DIVIDE FACTOR Q
ADC CLOCK FREQUENCY (MHz)
SAMPLE FREQUENCY (kHz)
Q
(2)
f
osc
/(2Q)
f
osc
/(256Q)
(3)
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