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參數(shù)資料
| 型號： | UCC2857 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Isolated Boost PFC Preregulator Controller |
| 中文描述： | 隔離升壓PFC前置穩(wěn)壓器控制器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 127K |
| 代理商： | UCC2857 |
7
UCC1857
UCC2857
UCC3857
The design of the boost inductor is very similar to the
conventional boost converter. However, as shown in the
Typical Application Circuit, an additional winding con-
nected to the output through a diode is required on the
boost inductor. This winding must have the same turns
ratio as the transformer and meet the isolation require-
ments. This winding is required to provide a discharge
path for the inductor energy when the push-pull switches
are both off. During start-up, when the output voltage is
zero, the converter can see very high inrush currents.
The overcurrent protection circuit of UCC3857 will shut
down all the outputs when the set threshold is crossed.
At that instance, the boost inductor auxiliary winding di-
rects the energy to the output. This is a preferred manner
of bringing the output voltage up to prevent the main
switches from handling the high levels of inrush current.
However, when the auxiliary winding is transferring the
power to the output, the voltage stress across QA be-
comes input voltage plus the reflected output volt-
age–higher than its steady state value of reflected output
voltage.
Chip Bias Supply and Start-up
UCC3857 is implemented using Unitrode’s BCDMOS
process which allows minimization of the start-up (60 A
typical) and operating (3.5mA typical) supply currents. It
results in significantly lower power consumption in the
trickle charge resistor used to start-up the IC.
Oscillator Set-up
The oscillator of UCC3857 is designed to have a wide
ramp amplitude (4.5V p–p) for higher noise immunity.
The CT pin has the sawtooth waveshape and during the
discharge time of C
T
, a clock pulse is generated. During
the discharge period, the effective internal impedance to
GND is 600 . Based on this, the discharge time is given
by 831
C
T
. As shown in the waveforms of Fig. 1, the in-
ternal clock pulse width is equal to the discharge time
and that sets the minimum dead time between IGDRV1
and IGDRV2. The clock frequency is given by
1
831
1 5
)
f
R
C
R
C
SW
T
T
T
T
=
+
≈
1
1 5
)
(1)
The IGDRV1 and IGDRV2 outputs are switched at half
the clock frequency while MOSDRV is switched at the
clock frequency.
Reference Signal (I
MULT
) generation
Like the UC3854 series, the UCC3857 has an analog
computation unit (ACU) which generates a reference cur-
rent signal for the current error amplifier. The inputs to
the ACU are signals proportional to instantaneous line
voltage, input voltage RMS information and the voltage
error amplifier output. Unlike prior techniques of RMS
voltage sensing, UCC3857 employs a patent pending
technique to simplify the RMS voltage generation and
eliminate
performance
degradation
previous techniques. With the novel technique (shown in
Fig. 3), need for external 2-pole filter for V
RMS
generation
is eliminated. Instead, the IAC current is mirrored and
used to charge an external capacitor (C
CRMS
) during a
half cycle. The voltage on CRMS takes the integrated si-
nusoidal shape and is given by equation 2. At the end of
the half-cycle, CRMS voltage is held and converted into
a 6-bit digital word for further processing in the ACU.
C
CRMS
is discharged and readied for integration during
next half cycle.
caused
by
the
The advantage of this method is that the second har-
monic ripple on the V
RMS
signal is virtually eliminated.
Such second harmonic ripple is unavoidable with the lim-
ited roll-off of a conventional 2-pole filter and results in
3rd harmonic distortion in the input current signal. The
dynamic response to the input line variations is also im-
proved as a new V
RMS
signal is generated every cycle.
I
pk
C
CRMS
2
ω
(
)
V
t
CRMS
AC
=
(
)
cos
1
ω
(2)
V
pk
(
I
pk
(
C
CRMS
AC
CRMS
)
)
=
ω
(2a)
For proper operation, I
AC
(pk) should be selected to be
100 A at peak line voltage. For universal input voltage
with peak value of 265 VAC, this means R
AC
= 3.6M. The
noise sensitivity of the IC requires a small bypass capaci-
tor for high frequency noise filtering. The value of this ca-
pacitor should be limited to 220nF maximum. The V
CRMS
value should be approximately 1V at the peak of low line
(80 VAC) to minimize any digitization errors. The peak
value of V
CRMS
at high line then becomes 3.5V. The de-
sired C
CRMS
can be calculated from equation 2 to be
75nF for 60Hz line.
The multiplier output current is given by equation (3) with
K = 0.33.
V
I
V
CRMS
I
K
MULT
VAO
AC
=
(
– . )
0 5
2
(3)
The multiplier peak current is limited to 200 A and the
selected values for I
AC
and V
CRMS
should ensure that
the current is within this range. Another limitation of the
multiplier is that I
MULT
can not exceed two times the IAC
current, limiting the minimum voltage on V
CRMS
.
The discrete nature of the RMS voltage feedforward
means that there are regions of operation where the in-
APPLICATION INFORMATION (cont.)
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