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參數(shù)資料
| 型號： | UCC2857 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Isolated Boost PFC Preregulator Controller |
| 中文描述： | 隔離升壓PFC前置穩(wěn)壓器控制器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 127K |
| 代理商： | UCC2857 |
5
UCC1857
UCC2857
UCC3857
output voltage regulation information to VA– across the
isolation barrier.
SS:
A capacitor is connected between SS and GND to
provide the UCC3857 soft start feature. The voltage on
VAO, is clamped to approximately the same voltage as
SS. An internal 10
μ
A (nominal) current source is pro-
vided by the UCC3857 to charge the soft start capacitor.
VD:
Positive supply rail for the three output driver stages.
The voltage applied to VD must be limited to less than
18VDC. VD should be bypassed to PGND with a 0.1
μ
F
to 1.0
μ
F low ESR, ESL capacitor for best results. VD and
VIN can be isolated from each other with an RC lowpass
filter for better supply noise rejection.
VIN:
Input voltage supply to the UCC3857. This voltage
must be limited to less than 18VDC. The UCC3857 is en-
abled when the voltage on VIN exceeds 13.75V (nomi-
nal).
VREF:
Output of the precision 7.5V reference. A 0.01
μ
F
to 0.1
μ
F low ESR, ESL bypass capacitor is recom-
mended between VREF and AGND for best perform-
ance.
PIN DESCRIPTIONS (continued)
V
CT
(PIN 20) &
V
CAO
(PIN 8)
CLOCK
(INTERNAL)
TOGGLE F/F Q
(INTERNAL)
IGDRV1
(PIN 16)
IGDRV2
(PIN 18)
MOSDRV
(PIN 14)
TD1
Figure 1. Typical control circuit timing diagram.
UDG-98217
APPLICATION INFORMATION
UCC3857 is designed to provide a solution for single
stage power factor correction and step-down or step-up
function, using an isolated boost converter. The Typical
Application Circuit shows the implementation of a typical
isolated boost converter using IGBTs as main switches in
push-pull configuration and using a MOSFET as an auxil-
iary switch to accomplish soft-switching of IGBTs. Many
variations of this implementation are possible including
bridge-type circuits. The presense of low frequency ripple
on the output makes this approach practical for distrib-
uted bus applications. It will not provide the highly regu-
lated low ripple outputs typically required by logic level
supplies.
The circuit shown in the Typical Application Circuit pro-
vides several advantages over a more conventional ap-
proach of deriving a DC bus voltage from AC line with
power factor correction. The conventional approach uses
two power conversion stages and has higher cost and
complexity. With the use of UCC3857, the dual function-
ality of power factor correction and voltage step-down is
combined into a single stage.
The power stage comprises a current-fed push-pull con-
verter where the ON times of the push-pull switches (Q1
and Q2) are overlapped to provide effective duty cycle of
a conventional PWM boost converter.
switch is on, the power is transferred to the output
When only one
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相關代理商/技術參數(shù) |
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