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參數(shù)資料
| 型號： | UCC2752N |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 電話鈴聲 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 103K |
| 代理商： | UCC2752N |
5
UCC2751
UCC3751
APPLICATION INFORMATION
Power Stage Operation
The power stage used for the UCC3751 application has
two distinct switching circuits which together produce the
required low frequency signal on the output. The primary
side switching circuit consists of a current fed push-pull
resonant circuit that generates the high frequency sinu-
soidal waveform across the transformer winding. The op-
eration of this type of circuit is extensively covered in
Unitrode Application notes U-141 and U-148. Resonant
components C
R1
, C
R2
, L
R
, N should be chosen so that
the
primary
and
secondary
matched. Also, for the UCC3751 operation, switching fre-
quency is fixed by crystal selection. So, the resonant
components must be selected to yield a resonant fre-
quency close enough to the switching frequency to get a
low distortion sine-wave. Practically, since it is impossi-
ble to get an exact match between the two frequencies,
the switching frequency should always be higher than
the resonant frequency to ensure low distortion and take
advantage of ZVT operation. Switches Q1 and Q2 are
pulsed at 50% duty cycle at the switching frequency
(89.489 kHz) determined by a crystal (3.579545 MHz)
connected to the UCC3751. The input voltage for the
resonant stage (typically 12V) determines the voltage
stress of Q1 and Q2. Transformer turns ratio is deter-
mined by the output voltage requirements. On the sec-
ondary side, the high frequency waveform is sampled at
a predetermined frequency (e.g. 89.469 kHz) which dif-
fers from the primary switching frequency by the desired
output frequency (e.g. 20 Hz). The sampling is accom-
plished using a bi-directional switching circuit as shown
in Figure 2 and Figure 3. Figure 2 shows the sampling
mechanism consisting of two back-to-back FET switches
allowing current flow in both directions. The sampling
can also be done with a single active switch and a
full-bridge rectifier as shown in Fig. 3. The DRVS pin of
the UCC3751 provides the drive signal for the sampling
switch(es) and this signal is coupled through a pulse
resonances
are
well
transformer. Typical pulsewidth of the sampling signal is
280ns. As a result of sampling, the resultant output signal
matches the secondary voltage in amplitude and has a
low output frequency desired for ring generation.
The secondary winding of the power transformer also has
a tap (or a separate winding) to generate a loosely regu-
lated DC voltage. This DC voltage can be used to offset
the ring generator output. The UCC3751 is also config-
ured such that the AC output can go to zero under certain
conditions. Table 2 provides the logic levels for different
operating modes of UCC3751. Operation in mode 2 is
achieved by altering the sampling frequency to match the
switching frequency and sampling the secondary AC volt-
age at zero crossings. As a result, the resultant total out-
put voltage between V
OUT
and GND is the semi-regulated
DC voltage achieved through the tapped secondary. This
feature allows the circuit to operate under off-hook and
idle conditions when only the DC portion of the voltage is
required. The activation of this mode occurs when the
OHD voltage exceeds a set threshold or RINGEN is low.
The incorporation of this mode eliminates any need for
external relays or switching circuits as well as eliminating
the need for an additional power supply for powering the
phone. The DC voltage level can be fine tuned by adjust-
ing the voltage on the DELAY pin of the UCC3751. This
pin sets the sampling delay time during the off-hook
mode and allows a DC voltage to be developed between
V
1
and V
OUT
during this mode. Fig. 1 illustrates the oper-
ation of this mode. When the DELAY is set between 0
and 1V, the sampling is done in phase with the primary
switching instances (at points A), leading to an average
voltage of 0V between V
1
and V
OUT
for a sinusoidal sec-
ondary signal. If DELAY is set to another level, the sam-
pling instance shifts
(e.g. to point B) leading to an
effective voltage VB being developed between V
1
and
V
OUT
. The actual V
OUT
is the sum of VB and the DC off-
set voltage derived from the additional (or tapped) wind-
ing (V
1
).
Condition
OHD
RINGEN
High
Low
Sampling Output Mode
Frequency Offset from Primary (Mode 1)
Synchronized to Primary Frequency with Phase
Controlled by DELAY (Mode 2)
Mode 2
Mode 1/Mode 2
Continuous Ringing
Idle (On Hook, No Ringing)
Low
Low
Off-Hook
Cadenced Ringing
High
Low
X (Low/High)
High/Low
Table II. Operating mode selection.
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