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參數(shù)資料
| 型號(hào)： | UCC2752N |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 電話鈴聲 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 103K |
| 代理商： | UCC2752N |
4
UCC2751
UCC3751
PIN DESCRIPTIONS
DCLIM:
Primary current sense input. Signal proportional
to the primary switch current. All outputs are turned off
when a threshold of 300mV is exceeded on this pin.
This current limit works on a cycle-by-cycle basis.
DELAY:
A resistive divider from VDD to GND is pro-
grammed and fed into DELAY pin. The voltage at this pin
sets the phase difference between the sampling pulses
and primary pulses under off-hook condition. By pro-
gramming the delay, desired level of DC voltage can be
attained at the ringer output when the OHD threshold is
exceeded.
DRV1, DRV2:
Low impedance driver outputs for the pri-
mary switches.
DRVS:
Low impedance driver output for the sampling
switch(es). The pulse width of this output is 280ns.
Typically, a pulse transformer is used to couple the short
sampling pulses at DRVS to the floating sampling
switch(es).
ENABLE:
Logic input which turns off the outputs when
low.
FS0, FS1:
Frequency select pins for determining the dif-
ference frequency between primary and secondary
pulses under normal operation. These pins can be hard-
wired to GND or VDD to get one of the available output
frequencies (20,25 and 50 Hz). See Note 1 in the spec
table.
GND:
Reference point for all the internal voltages and
common return for the device.
OHD:
Secondary current sense input. Voltage propor-
tional to output current DC level is fed into this pin and
compared to an internal threshold of 300mV. If the thresh-
old is exceeded, the sampling scheme is changed to
eliminate the AC component in the output voltage as re-
quired by the off-hook condition.
PGND:
Return point for the output drivers. Connect to
GND at a single point in the circuit.
RINGEN:
Logic input used to determine when the ring
signal is needed. When this signal is high and OHD low,
normal ring signal is available at the output of the ring
generator.
VDD:
Internal regulated 5V supply. This voltage is used to
power all the internal precision circuits of the IC. This pin
needs to be bypassed to GND with ceramic capacitor.
VS12:
External 12V power supply for the IC. Powers V
DD
and provides voltage for the output drivers.
XTAL1, XTAL2:
Pins for connecting precision Crystal to
attain the accurate output frequencies. An external
square-wave pulse can also be applied to XTAL2 if XTAL1
is tied to VDD/2.
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications hold for T
A
= 0°C to 70°C for the
UCC3751 and –40°C to +85°C for the UCC2751, T
A
= T
J
.
PARAMETER
Off-Hook Sampling Delay (Note 2)
td0
V
DELAY
< 0.9V
td1
1.1V < V
DELAY
< 1.9V
td2
2.1V < V
DELAY
< 2.9V
td3
3.1V < V
DELAY
< 3.9V
td4
4.1V < V
DELAY
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0
20
308
616
924
1232
nS
nS
nS
nS
nS
252
504
756
1008
280
560
840
1120
Note 1.
Frequency setting is as shown in the Frequency Selectability Decoding Table. Sine Wave Frequency = Primary – Sampling
Frequency.
Note 2.
The delay function will delay the sample pulse from the rising edge of DRV2 to allow adjustment of the DC level provided
during Mode 2.
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