參數(shù)資料
型號(hào): UCB1400
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Audio codec with touch screen controller and power management monitor
中文描述: 音頻編解碼器與觸摸屏控制器和電源管理監(jiān)控
文件頁數(shù): 9/63頁
文件大?。?/td> 674K
代理商: UCB1400
Philips Semiconductors
UCB1400
Audio codec with touch screen controller
and power management monitor
Product data
Rev. 02 — 21 June 2002
9 of 63
9397 750 09611
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
SDAT_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit
positions stuffed with 0s by the AC ’97 Controller. If there are less than 20 valid bits
within an assigned and valid time slot, the AC ’97 Controller always stuffs all trailing
non-valid bit positions of the 20-bit slot with 0s.
Slot 1: Command address port:
The command port is used to control features, and
monitor status (see
Section 8.3.3 “AC-link audio input frame (SDATA_IN)”
, Slots 1
and 2) for AC ’97 functions including, but not limited to, sample rate, codec
configuration, and power management.
The control interface architecture supports up to 64 16-bit read/write registers,
addressable on even byte boundaries, and reserves support for 64 odd addresses, as
described in AC ’97 2.1 Component Specification Appendix D Only the even
registers (00h, 02h, etc.) are currently defined, odd register (01h, 03h, etc.) accesses
are reserved.
Note that shadowing of the control register file on the AC ’97 Controller is an option
left open to the implementation of the AC ’97 Controller. UCB1400’s control register
file is readable as well as writable to provide more robust testability.
Audio output frame slot 1 communicates control register address, and write/read
command information to the UCB1400.
Command Address Port bit assignments are:
Bit(19) Read/write command (1 = read, 0 = write).
Bit(18:12) Control register index (64 16-bit locations, addressed on even byte
boundaries)
Bit(11:0) Reserved (stuffed with 0s)
The first bit (MSB) sampled by UCB1400 indicates whether the current control
transaction is a read or a write operation. The following 7 bit positions communicate
with the targeted control register address. The trailing 12 bit positions within the slot
are reserved and must be stuffed with 0s by the AC ’97 Controller.
Fig 7.
Start of an audio output frame.
SYNC
BIT_CLK
SDATA_OUT
END OF PREVIOUS
AUDIO FRAME
slot(1)
slot(2)
SN00222
VALID
FRAME
AC ’97 SAMPLES SYNC ASSERTION HERE
AC ’97 SAMPLES FIRST SDATA_OUT BIT OF FRAME HERE
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