參數(shù)資料
型號(hào): UCB1400
廠商: NXP Semiconductors N.V.
元件分類: Codec
英文描述: Audio codec with touch screen controller and power management monitor
中文描述: 音頻編解碼器與觸摸屏控制器和電源管理監(jiān)控
文件頁數(shù): 6/63頁
文件大?。?/td> 674K
代理商: UCB1400
Philips Semiconductors
UCB1400
Audio codec with touch screen controller
and power management monitor
Product data
Rev. 02 — 21 June 2002
6 of 63
9397 750 09611
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
8.
AC ’97 interface
The UCB1400 implements an AC ’97 Revision 2.1 interface. Refer to the Audio
Codec ’97 Component Specification Revision 2.1from Intel.
8.1 Clocking
The UCB1400 functions only as a primary codec. As such, it derives its clock
internally from an externally attached 24.576 MHz crystal or clock oscillator, and
drives a buffered and divided down (
1
2
) clock to its digital companion controller over
AC-link under the signal name “BIT_CLK”.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-link
is synchronized to the rising edge of the SYNC signal. SYNC is driven by the AC ’97
Controller. The AC ’97 Controller takes BIT_CLK as an input and generates SYNC by
dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This
yields a 48 kHz SYNC signal whose period defines an audio frame. Data is
transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled
on the receiving side of AC-link on each immediately following falling edge of
BIT_CLK.
8.2 Resetting UCB1400
The UCB1400 recognizes the following types of reset:
Cold reset: where all UCB1400 logic (registers included) is initialized to its default
state. Initiated by bringing RESET LOW for at least 1
μ
s.
Warm reset: where the contents of the UCB1400 register set are left unaltered.
Initiated by bringing SYNC HIGH for at least 1
μ
s without BIT_CLK.
Register reset: which only initializes the UCB1400 registers to their default states.
Initiated by a write to register 0x00.
After signaling a reset to UCB1400, the AC ’97 Controller should not attempt to play
or capture audio data until it has sampled a “Codec Ready” indication from UCB1400.
Fig 4.
UCB1400 and AC ’97 controller connection diagram.
SN00237
UCB1400
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET
IRQOUT
AC97
CONTROLLER
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