參數(shù)資料
型號: UC2872M
英文描述: Intelligent quad (2 x 5A/2 x 2.5A) low-side switch
中文描述: 功率因數(shù)控制器
文件頁數(shù): 6/10頁
文件大小: 352K
代理商: UC2872M
6
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
ISNS+:
This is the non-inverting input to the X10 instru-
mentation amplifier. The common mode input range for
this pin extends from GND to VCC.
ISOUT:
This is the output of the X10 instrumentation am-
plifier. The output voltage on this pin is level shifted 2V
above GND, such that if a 100mV differential input is ap-
plied across ISNS+ and ISNS–, the output will be 3V.
PGND:
This is the high current ground for the IC. The
MOSFET driver transistors are referenced to this ground.
For best performance an external star ground connection
should be made between this pin, the source of the low
side MOSFET, the capacitor on CAP, the anodes of any
external Schottky clamp diodes and the output filter ca-
pacitor. As with all high frequency layouts, a ground plane
and short leads are highly recommended.
SS:
A capacitor from this pin to GND in conjunction with
an internal 10 A current source provides a soft start
function for the IC. The voltage level on SS clamps the
output of the voltage amplifier through an internal buffer,
thus providing a controlled startup. The SS time is ap-
proximately:
C
V
V
V
3
A
SS
O
IN
10
μ
Once the device has completed its soft start cycle, a low
power sleep mode can be invoked by pulling SS below
0.5V typically. In sleep mode, all of the device functions
are disabled except for those which are required to bring
the device out of sleep mode when SS is released. Typi-
cal sleep mode supply current is less than 50mA.
VCC:
Positive supply rail for the IC. Bypass this pin to
GND with a 1mF low ESL/ESR ceramic capacitor. The
maximum voltage for VCC is 36V. The turn on voltage
level on VCC is 4.5V with 100mV of hysteresis for the
UC3870-1 and 10V with 1V of hysteresis for the
UC3870-2.
VREF:
V
REF
is the output of the precision reference.
The output is capable of supplying 20mA to peripheral
circuitry and is internally short circuit current limited.
VREF is disabled and low whenever VCC is below the
UVLO threshold, and when SS is pulled below 0.5V. A
VREF “good” comparator senses VREF and disables the
PWM stage until VREF has attained approximately 90%
of its nominal value. Bypass VREF to GND with a 0.1mF
ceramic capacitor for best performance.
VSNS:
This pin is the inverting input of the voltage am-
plifier and serves as the output voltage feedback point
for the synchronous regulator. It senses the output volt-
age through a voltage divider which produces a nominal
2V.
PIN DESCRIPTIONS (continued)
The UC3870 employs a fixed frequency average current
mode control buck topology to convert a higher battery
voltage down to a tightly regulated output voltage.
cial design techniques allow this bipolar IC to deliver ex-
ceptional performance while consuming approximately
6mA of supply current over an input voltage range of 4.5
to 35 volts. Fixed frequency operation allows synchroni-
zation to an existing system clock, and easier filtering.
Average current mode control provides inherent slope
compensation and accurate short circuit current limiting.
Spe-
The output inductor current is sensed by an external low
value shunt resistor (R
SENSE
).
current should be no larger than 100mV in order to mini-
mize sensing losses. The differential voltage across
Rsense is amplified by the internal X10 instrumentation
amplifier. The common mode input range for this ampli-
fier extends from GND to VCC in order to maintain accu-
rate current sensing under normal conditions as well as
abnormal conditions such as output short circuit and low
This signal at full load
drop
instrumentation amplifier is applied to the inverting input
of the current amplifier through an external resistor. The
converter’s output voltage feedback is applied to the
VSNS pin through an external voltage divider. The differ-
ence between the voltage at VSNS and the voltage at
the non-inverting input is amplified by the voltage ampli-
fier and applied to the non-inverting input of the current
amplifier. This instantaneous reference level forms the
current command input for the average current control
loop. The average current amplifier develops the duty cy-
cle command signal by integrating the current feedback
signal with respect to the instantaneous current com-
mand input. This output is compared to the fixed high
amplitude oscillator ramp waveform at the inputs of the
PWM comparator to develop duty cycle information for
the PWM drive. The large amplitude oscillator ramp pro-
vides both high noise margin and built-in slope compen-
sation in average current mode control methodology.
The fixed frequency oscillator is programmed with a sin-
out
(LDO)
modes.
The
output
of
the
X10
APPLICATIONS INFORMATION
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