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參數(shù)資料
| 型號： | UC2872M |
| 英文描述： | Intelligent quad (2 x 5A/2 x 2.5A) low-side switch |
| 中文描述： | 功率因數(shù)控制器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 352K |
| 代理商： | UC2872M |
5
UC1870 -1/ -2
UC2870 -1/ -2
UC3870 -1/ -2
BOOT:
This pin provides the high side rail for the
HDRIVE
output.
An
external
connected between this pin and the drain of the external
low side MOSFET.
When the low side MOSFET is
conducting Cbst is charged to 11V (UC3870-2), 7.5V
(UC3870-1), via an external diode tied to CAP. When the
low side MOSFET turns off and the high side MOSFET
turns on, the Cbst bootstraps itself up with the source of
high side MOSFET, ultimately providing a 10V Vgs for
the upper MOSFET. Since this 10V is referenced to the
source of the high side N-channel MOSFET, the actual
voltage on BOOT and HDRIVE is approximately 10V
above VCC while the high side MOSFET is conducting.
The voltage on BOOT is continuously monitored during
low input voltage conditions when the duty cycle equals
approximately 100% to insure that a sufficient gate drive
level is being supplied by the UC3870. If the voltage on
BOOT falls below 8V (UC3870-2) or 3.5V (UC3870-1),
the IC forces the low side driver to cycle itself on for the
few cycles required to replenish Cbst. In this way, virtual
100% duty cycle operation is provided.
capacitor
(Cbst)
is
CA-:
This is the inverting input to the current amplifier.
Connect a series resistor and capacitor between this pin
and CAO to set the current loop compensation. An input
resistor between this pin and ISOUT provides the induc-
tor current sense signal to the amplifier and also sets the
high frequency gain of the amplifier. The common mode
operating range for this input is between GND and 4V.
The normal range during operation is between 2V and
3V.
CAO:
This is the output of the wide bandwidth current
amplifier and one of the inputs to the PWM duty cycle
comparator. The output signal generated by this amplifier
commands the PWM to force the correct duty cycle to
maintain output voltage in regulation. The output can
swing from 0.1V to 4V.
CAP:
A capacitor is normally connected between this pin
and
GND
providing
bypass
(UC3870-2) and 7.5V (UC3870-1) regulator. Charge is
transferred from this capacitor to Cbst via an external di-
ode when the low side MOSFET is conducting. If VCC
≤
10V logic level MOSFETs are generally specified. CAP
should then be shorted to VCC in conjuncton with a low
VF Schottky to BOOT to maximize the gate drive ampli-
tude. This technique provides adequate gate drive signal
amplitudes with VCC as low as 4.5V. For high input volt-
age applications, a simple external shunt zener regulator
circuit can be connected to CAP, thereby offloading
power dissipation requirements from the IC to an external
transistor.
for
the
internal
11V
COMP:
This is the output of the voltage amplifier. It pro-
vides the current command signal to the current ampli-
fier. The voltage is clamped to approximately 3.2V.
CMD:
This is the non-inverting input of the voltage error
amplifier. The voltage applied to CMD sets the output
voltage of the power converter. The 2V to 3.5V input
common mode range allows for direct interfacing to the
UC3910 DAC/precision reference.
CT:
A capacitor from CT to GND sets the PWM oscillator
frequency according to the following equation:
1
14250
F
CT
.
Use a high quality ceramic capacitor with low ESL and
ESR for best results. A minimum CT value of 220pF in-
sures good accuracy and less susceptibility to circuit lay-
out parasitics. The oscillator and PWM are designed to
provide practical operation to 300kHZ.
GND:
All voltages are measured with respect to this pin.
All bypass capacitors and timing components except
those listed under the PGND pin description should be
connected to this pin. Component leads should be as
short and direct as possible.
HDRIVE, LDRIVE:
The outputs of the PWM are totem
pole MOSFET gate drivers on the HDRIVE and LDRIVE
pins. The outputs can sink approximately 1A and source
500mA. This characteristic optimizes the switching tran-
sitions by providing a controlled dV/dT at turn-on and a
lower impedance at turn-off. These are complementary
outputs with a typical deadtime of 200ns. Internal cir-
cuitry prevents the possibility of simultaneous conduction
of the output MOSFETs (shoot through). HDRIVE is the
high side bootstrapped output. Its upper power supply
rail is the BOOT pin which means that its output will fly
approximately 10V above VCC when the upper side of
the totem pole output is conducting. The power supply
rail for LDRIVE is CAP. As a result the Vgs of both gates
are regulated to approximately 10V if VCC is >11V. A
series resistor between these pins and the MOSFET
gates of at least 10 ohms can be used to control ringing.
Additionally, a low VF Schottky diode should be
nected between these pins and GND to prevent sub-
strate conduction and possible erratic operation.
con-
ISNS–:
This is the inverting input to the X10 instrumen-
tation amplifier. The common mode input range for this
pin extends from GND to VCC. A low value resistor in
series with the output inductor is connected between this
pin and ISNS+ to develop the current sense signal.
PIN DESCRIPTIONS
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