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參數(shù)資料
| 型號： | UC2548 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Primary Side PWM Controller |
| 中文描述： | 一次側(cè)PWM控制器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 345K |
| 代理商： | UC2548 |
UC1548
UC2548
UC3548
Pulse width modulation is achieved by comparing the out-
put of the current error amplifier to the feed forward ramp
generated at VS (Figure 7). The charge slope of the ramp
is determined by a resistor (RVS) from VS to VIN and a
capacitor (CVS) from VS to GND. In the event that CAO is
at its maximum voltage, typically 3.3V, the UC3548 will
limit the power stage to a volt-second product of:
V
IN
T
ON
(max) = 3.3V
Rvs
Cvs.
An isolated voltage control loop can be implemented with
a secondary side reference, error amplifier and an opto-
isolator. The optoisolator can be used to override the
current amplifier output which is current limited by a 2.5k
resistor. In overcurrent situations, the voltage loop turns
the optoisolator off and the current error amplifier then as-
sumes duty cycle control resulting in accurately limited
maximum output current.
A patented technique is used to accurately program maxi-
mum duty cycle. Programming is accomplished by a
divider from VREF to DMAX (Figure 7). The value pro-
grammed is:
D(max) = Rd1 / (Rd1 + Rd2).
For proper operation, the integrating capacitor, C
DC
,
should be larger than T(osc) / 80k, where T(osc) is the os-
cillator period. C
DC
also sets the soft start time constant,
so values of C
DC
larger than minimum may be desired.
The soft start time constant is approximately:
T(ss) = 20k
C
DC
.
The output driver on the UC3548 is capable of 2A peak
currents. Careful layout is essential for correct operation
of the chip. A ground plane must be employed (Figure 8).
A unique section of the ground plane must be designated
for high di/dt currents associated with the output stage.
This point is the power ground to which to PGND pin is
connected. Power ground can be separated from the rest
of the ground plane and connected at a single point, al-
though this is not strictly necessary if the high di/dt paths
are well understood and accounted for. VCC should be
bypassed directly to power ground with a good high fre-
quency capacitor. The source of the power MOSFET
should connect to power ground as should the return con-
nection for input power to the system and the bulk input
capacitor. The output should be clamped with a high cur-
rent Schottky diode to both VCC and PGND. Nothing else
should be connected to power ground.
VREF should be bypassed directly to the signal portion of
the ground plane with a good high frequency capacitor.
Low ESR/ESL ceramic 1
μ
F capacitors are recommended
for both VCC and VREF. The capacitors from CT, CDC, CI
and VS should likewise be connected to the signal ground
plane.
FEED FORWARD PULSE WIDTH MODULATION
MAXIMUM DUTY CYCLE AND SOFT START
GROUND PLANES
Figure 7:
Duty Cycle Control
UDG-95044
UDG-95045-1
7
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