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參數(shù)資料
| 型號： | UC2548 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Primary Side PWM Controller |
| 中文描述： | 一次側(cè)PWM控制器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 345K |
| 代理商： | UC2548 |
UC1548
UC2548
UC3548
Figure 1:
Undervoltage Lockout
UDG-95038
Figure 2:
Oscillator Frequency
20
100
1000
2000
100
1000
5000
C (pF)
500
50
500
Oscillator Frequency as a Function of CT
Frequency Decrease as a Function of RT
RT = Open
UDG-95039
The undervoltage lockout block diagram is shown in Fig-
ure 1. The VCC comparator monitors chip supply voltage.
Hysteretic thresholds are set at 13V and 10V to facilitate
off-line applications. If the VCC comparator is low, ICC is
low (<500
μ
A) and the output is low.
The UV comparator monitors input line voltage (V
IN
). A
pair of resistors divides the input line to UV. Hysteretic in-
put line thresholds are programmed by Rv1 and Rv2. The
thresholds are
V
IN
(on) = 4.35V
(1 + Rv1/Rv2
′
) and
V
IN
(off) = 4.35V
(1 + Rv1/Rv2) where
Rv2
′
= Rv2
||
90k.
The resulting hysteresis is
V
IN
(hys) = 4.35V
Rv1 / 90k.
When the UV comparator is low, I
CC
is low (<500
μ
A) and
the output is low.
When both the UV and VCC comparators are high, the in-
ternal bias circuitry for the remainder of the chip is
activated. The CDC pin (see discussion on Maximum Duty
Cycle Control and Soft Start) and the Output are held low
until VREF exceeds the 4.5V threshold of the VREF com-
parator. When VREF is good, control of the output driver is
transferred to the PWM circuitry and CDC is allowed to
charge.
If any of the three UVLO comparators go low, the UVLO
latch is set, the output is held low, and CDC is discharged.
This state will be maintained until all three comparators are
high and the CDC pin is fully discharged.
UNDERVOLTAGE LOCKOUT
4
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