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參數(shù)資料
| 型號： | UC2548 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Primary Side PWM Controller |
| 中文描述： | 一次側(cè)PWM控制器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 345K |
| 代理商： | UC2548 |
UC1548
UC2548
UC3548
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Duty Cycle Clamp
Max Duty Cycle
VCC Comparator
Turn-on Threshold
Turn-off Threshold
Hysteresis
UV Comparator
Turn-on Threshold
R
HYSTERESIS
Reference
VREF
V(D
MAX
) = 0.75
V
REF
73.5
76.5
79.5
%
13
10
3
14
V
V
V
9
2.5
3.5
4.1
77
4.35
90
4.6
103
V
k
Vuv = 4.2V
T
A
= 25
°
C
0
<
I
O
<
10mA, 12
<
VCC
<
20
12V < V
CC
< 20V
0 < I
O
< 10mA
V
REF
= 0V
4.95
4.93
5
5.05
5.07
15
15
70
V
V
Line Regulation
Load Regulation
Short Circuit Current
Output Stage
Rise & Fall Time (Note 1)
Output Low Saturation
4
3
50
mV
mV
mA
30
Cl = 1nF
I
O
= 20mA
I
O
= 200mA
I
O
= -200mA
I
O
= 20mA
20
0.25
1.2
2.0
0.8
45
0.4
2.2
3.0
1.2
ns
V
V
V
V
Output High Saturation
UVLO Output Low Saturation
I
CC
I
START
I
CC
(pre-start)
I
CC
(run)
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
VCC = 12V
VCC = 15V, V(UV) = 0
0.2
0.5
22
0.4
1
26
mA
mA
mA
ELECTRICAL CHARACTERISTICS (cont.):
Unless otherwise stated, all specifications are over the junction
temperature range of
55
°
C to +125
°
C for the UC1548,
40
°
C to +85
°
C for the UC2548, and 0
°
C to +70
°
C for the UC3548. Test
conditions are: VCC = 12V, CT = 400pF, CI = 100pF, IOFF = 100
μ
A, CDC = 100nF, Cvs = 100pF, and Ivs = 400
μ
A, T
A
= T
J
.
CAO:
Output of the current error amplifier. Also the
resistor load for the collector of an optocoupler.
CDC:
Connect a charge balance integration capacitor
from CDC to GND to achieve an accurate duty cycle
clamp. This capacitor also sets the soft start time.
CI:
Output of the inductor current waveform synthesizer.
Requires a capacitor to ground.
CT:
A capacitor from CT to GND sets the oscillator
frequency.
DMAX:
Programs maximum duty cycle with a resistive
divider from VREF to DMAX to GND.
GND:
Signal ground.
INV:
Inverting input of the current error amplifier.
IOFF:
Programs the discharge slope of the capacitor on
CI to emulate the down slope of the inductor current
waveform.
ION:
Input pin to inductor current waveform synthesizer.
Apply a voltage proportional to switch current to this pin.
NI:
Noninverting input of the current error amplifier.
OUT
: Output driver for the gate of a power FET.
PGND:
Power ground pin for the output driver. This
ground circuit should be connected to GND at a single
point.
UV:
Line voltage sense pin to insure the chip only
operates with sufficient line voltage. Program with a
resistive divider from the converter input voltage to UV
to GND.
VCC:
Chip supply voltage. Bypass with a 1
μ
F ceramic
capacitor to PGND.
VREF:
Precision voltage reference. Bypass with a 1
μ
F
ceramic capacitor to GND.
VS:
Volt second clamp programming pin and feedforward
ramp waveform for the pulse width modulator. Connect a
resistor to the input line voltage and a capacitor to GND.
3
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