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參數(shù)資料
| 型號(hào)： | UC1914 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 5V to 35V Hot Swap Power Manager |
| 中文描述： | 5V至35V的熱插拔電源管理器 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 652K |
| 代理商： | UC1914 |
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UC1914
UC2914
UC3914
Figure 3a: Typical timing diagram.
UDG-97054
t0: N
ormal conditions - output current is nominal, output
voltage is at positive rail, VCC
t1:
Fault control reached - output current rises above the
programmed fault value, C
T
begins to charge with
100
μ
A + I
PL
.
t2: M
aximum current reached - output current reaches
the programmed maximum level and becomes a con-
stant current with value IMAX.
t3:
Fault occurs - C
T
has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current
to flow, VOUT discharge to GND.
t4:
Retry - C
T
has discharged to 0.5V, but fault current
is still exceeded, C
T
begins charging again, FET is on,
VOUT increases.
t5 = t3:
Illustrates <3% duty cycle depending upon
R
PL
selected.
t6 = t4
t7 = t0:
Fault released, normal condition - return to
normal operation of the hot swap power manager.
Fig. 3a shows typical fault timing waveforms for the ex-
ternal NMOS output current, the voltage on the CT pin,
and the output load voltage, V
OUT
, with LR left floating or
grounded. The output voltage waveforms have assumed
an RC characteristic load and time constants will vary de-
pending upon the component values. Prior to time t
0
, the
load is fully charged to almost VCC and the NMOS is
supplying the current, I
O
, to the load. At t
0
, the current
begins to ramp up due to a change in the load conditions
until, at t
1
, the fault current level, I
FAULT,
has been
reached to cause switch S1 to close. This results in C
T
being charged with the current sources I1 and I
PL
. Dur-
ing this time, V
OUT
is still almost equal to VCC except for
small losses from voltage drops across the sense resis-
tor and the NMOS. The output current reaches the pro-
grammed maximum level, I
MAX,
at t
2
. The C
T
voltage
continues to rise since I
MAX
is still greater than I
FAULT
.
The load output voltage drops because the current load
requirements have become greater than the controlled
maximum sourcing current. The C
T
voltage reaches the
upper comparator threshold (Fig. 2) of 2.5V at t
3
, which
promptly shuts off the gate drive to the NMOS (not
APPLICATION INFORMATION (cont.)
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