
10
UC1914
UC2914
UC3914
Overload Comparator
The linear amplifier in the UC3914 ensures that the ex-
ternal NMOS does not source more than the current
I
MAX
, defined above as:
VCC
V
R
SENSE
I
MAX
IMAX
=
In the event that output current exceeds the programmed
I
MAX
by more than 200mV/R
SENSE,
the output of the lin-
ear amplifier will immediately be pulled low (with respect
to VOUTS) providing no gate drive to the NMOS, and
preventing current from being delivered to the load. This
situation could occur if the external NMOS is not re-
sponding to a command from the IC or output load condi-
tions change quickly to cause an overload condition
before the linear amplifier can respond. For example, if
the NMOS is sourcing current into a load and the load
suddenly becomes short circuited, an overload condition
may occur. The short circuit will cause the V
GS
of the
NMOS to immediately increase, resulting in increased
load current and voltage drop across R
SENSE.
If this drop
exceeds the overload comparator threshold, the amplifier
output will be quickly pulled low. It will also cause the CT
pin to begin charging with I3, a 3mA current source (refer
to Fig. 2) and continue to charge until approximately one
volt below VCC, where it is clamped. This allows a con-
stant fault to show up on FAULT and since the voltage on
CT will only charge past 2.5V in an overload fault condi-
tion, it can be used for detection of output NMOS failure
or to build redundancy into the system.
Estimating Minimum Timing Capacitance
The startup time of the IC may not exceed the fault time
for the application. Since the timing capacitor, C
T
, deter-
mines the fault time, its minimum value can be deter-
mined by calculating the startup time of the IC. The
startup time is dependent upon several external compo-
nents. A load capacitor, C
LOAD
, should be tied between
VOUTS and GND. Its value should be greater than that
of C
PUMP,
the reservoir capacitor tied from V
PUMP
to
V
OUTS
(see Fig. 4). Given values of C
LOAD,
Load,
R
SENSE
, VCC and the resistors determining the voltage
on I
MAX
, the user can calculate the approximate startup
time of the node V
OUT.
This time must be less than the
time it takes for C
T
to charge to 2.5V. Assuming the user
has determined the fault current, R
SENSE
can be calcu-
lated by:
mV
I
FAULT
R
SENSE
=
50
I
MAX
is the maximum current the UC3914 will allow
through the transistor M1. During startup with an output
capacitor, M1 can be modeled as a constant current
source of value I
MAX
where:
VCC
V
R
SENSE
I
MAX
IMAX
=
Given this information, calculation of startup time is now
possible via the following:
Current Source Load:
T
C
I
MAX
VCC
I
LOAD
START
LOAD
=
–
Resistive Load:
T
R
C
n
VCC
R
I
START
LOAD
LOAD
MAX
LOAD
=
l
1
The only remaining external component which may af-
fect the minimum timing capacitor is the optional power
limiting resistor, R
PL
. If the addition of R
PL
is desirable,
its value can be determined from the “Fault Timing” sec-
tion above. The minimum timing capacitor values are
now given by
Current Source Load:
CT
T
R
VCC
2
R
START
PL
PL
min
=
+
10
2
4
APPLICATION INFORMATION (cont.)
Figure 4. Estimating minimum timing capacitor.
UDG-97056