參數(shù)資料
型號: UC1682TFBZ
廠商: Electronic Theatre Controls, Inc.
英文描述: HIGH-VOLTAGE MIXED-SIGNAL IC
中文描述: 高電壓混合信號集成電路
文件頁數(shù): 7/70頁
文件大?。?/td> 1161K
代理商: UC1682TFBZ
UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
5
P
IN
D
ESCRIPTION
Name
Type
Pins
Description
M
AIN
P
OWER
S
UPPLY
V
DD
V
DD2
V
DD3
PWR
V
DD2
/V
DD3
is the analog power supply and it should be connected to the
same power source. V
DD
is the digital power supply and it should be
connected to a voltage source that is no higher than V
DD2
/V
DD3
.
Please maintain the following relationship:
V
DD
+1V
V
DD2/3
V
DD
.
"
Minimize the trace resistance for V
DD
and V
DD2
/V
DD3
.
V
SS
V
SS2
GND
Ground. Connect V
SS
and V
SS2
to the shared GND pin.
Minimize the trace resistance for this node.
LCD P
OWER
S
UPPLY
& V
OLTAGE
C
ONTROL
V
BIAS
I
This is the reference voltage to generate the actual SEG driving voltage.
V
BIAS
can be used to fine tune V
LCD
by external variable resistors.
Internal resistor network has been provided to simplify external trimming
circuit. The following network is sufficient for most applications.
An internal RC filter is provided to filter noise on the V
BIAS
pin. When not
used, it is OK to leave V
BIAS
open circuit. If noise starts to cause
problem, connect a small bypass capacitor between V
BIAS
and V
SS
.
In the OTP version, this pin is disconnected from internal circuit. So,
there is no need to add bypass capacitor for this pin for OTP version.
V
B1+
V
B1–
V
B0+
V
B0–
PWR
LCD Bias Voltages. These are the voltage sources to provide SEG
driving currents. These voltages are generated internally. Connect
capacitors of C
BX
value between V
BX+
and V
BX–
.
The resistance of these traces directly affects the driving strength of
SEG electrodes and impacts the image of the LCD module. Minimize
the trace resistance is critical in achieving high quality image.
S
B1+
S
B1–
S
B0+
S
B0–
I
Wire to corresponding V
B1/2x
pin. Merge ITO traces between
corresponding S
Bx
and V
Bx
in COG.
V
LCD-IN
V
LCD-OUT
PWR
High voltage LCD Power Supply. Connect these pins together.
By-pass capacitor C
L
is optional. It can be connected between V
LCD
and
V
SS
. When C
L
is used, keep the trace resistance under 300
.
N
OTE
Recommended capacitor values:
C
B
: 150~250x LCD load capacitance or 2.2μF (2V), whichever is higher.
C
L
: (Optional) 5nF~50nF (16V) is appropriate for most applications.
1M/VR
V
DD2
/ V
DD3
V
BIAS
330K
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