- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381146 > UC1682TFBZ (Electronic Theatre Controls, Inc.) HIGH-VOLTAGE MIXED-SIGNAL IC PDF資料下載
參數(shù)資料
| 型號(hào)： | UC1682TFBZ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HIGH-VOLTAGE MIXED-SIGNAL IC |
| 中文描述： | 高電壓混合信號(hào)集成電路 |
| 文件頁數(shù)： | 44/70頁 |
| 文件大?。?/td> | 1161K |
| 代理商： | UC1682TFBZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
U
LTRA
C
HIP
High-Voltage Mixed-Signal IC
1999 ~
2003
42
ES Specifications
D
ISPLAY
D
ATA
RAM
D
ATA
O
RGANIZATION
The input display data (depend on color mode)
are stored to a dual port static RAM (RAM, for
Display Data RAM) organized as 80x104X12.
After setting CA and RA, the subsequent data
write cycles will store the data for the specified
pixel to the proper memory location.
Please refer to the map in the following page
between the relation of COM, SEG, SRAM, and
various memory control registers.
D
ISPLAY
D
ATA
RAM A
The Display RAM is a special purpose dual port
RAM which allows asynchronous access to both
its column and row data. Thus, RAM can be
independently accessed both for Host Interface
and for display operations.
D
ISPLAY
D
ATA
RAM A
DDRESSING
A Host Interface (HI) memory access operation
starts with specifying Row Address (RA) and
Column Address (CA) by issuing
Set Row
Address
and
Set Column Address
commands.
If wrap-around (WA, AC[0]) is OFF (0), CA will
stop incrementing after reaching the end of row
(103), and system programmers need to set the
values of RA and CA explicitly.
If WA is ON (1), when CA reaches the end of a
row, CA will be reset to 0 and RA will increment
or decrement, depending on the setting of row
Increment Direction (RID, AC[2]). When RA
reaches the boundary of RAM (i.e. RA = 0 or 79),
RA will be wrapped around to the other end of
RAM and continue.
MX I
MPLEMENTATION
Column Mirroring (MX) is implemented by
selecting either (CA) or (103–CA) as the RAM
column address. Changing MX affects the data
written to the RAM.
Since MX has no effect on the data already
stored in RAM, changing MX does not have
immediate effect on the displayed pattern. To
refresh the display, refresh the data stored in
RAM after setting MX.
R
OW
M
APPING
COM electrode scanning orders are not affected
by Start Line (SL), Fixed Line (FL) or Mirror Y
(MY, LC[3]). Visually, register SL having a non-
zero value is equivalent to scrolling the LCD
display up or down (depends on MY) by
SL
rows.
RAM A
DDRESS
G
ENERATION
The mapping of the data stored in the display
SRAM and the scanning COM electrodes can be
obtained by combining the fixed COM scanning
sequence and the following RAM address
generation formula.
When FL=0, during the display operation, the
RAM line address generation can be
mathematically represented as following:
For the 1
st
line period of each field
Line = SL
Otherwise
Line =
Mod(
Line
+1, 80)
Where Mod
is the modular operator, and
Line
is
the bit slice line address of RAM to be outputted
to SEG drivers. Line 0 corresponds to the first bit-
slice of data in RAM.
The above
Line
generation formula produces the
“l(fā)oop around” effect as it effectively resets
Line
to
0 when
Line+1
reaches
80
. Effects such as
scrolling can be emulated by changing SL
dynamically.
MY I
MPLEMENTATION
Row Mirroring (MY) is implemented by reversing
the mapping order between COM electrodes and
RAM, i.e. the mathematical address generation
formula becomes:
For the 1
st
line period of each field
Line =
Mod(
SL + MUX-1
,
80
)
where MUX = CEN + 1
Otherwise
Line =
Mod(
Line-1
,
80
)
Visually, the effect of MY is equivalent to flipping
the display upside down. The data stored in
display RAM are not affected by MY.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UC1682THCZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682XFBZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682XHCZ | HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1834LQMLV | High Efficiency Linear Regulator |
| UC1834JQMLV | High Efficiency Linear Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UC1682THCZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682THDG | 制造商:Tianma Micro-electronics Co 功能描述:IC FOR TM9664FKFWG-11 - Bulk |
| UC1682XFBZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1682XHCZ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH-VOLTAGE MIXED-SIGNAL IC |
| UC1697V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128 x 128RGB C-STN LCD Controller-Driver w/ 16-bit per RGB On-Chip SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。