參數(shù)資料
型號： TZA3034U
廠商： NXP SEMICONDUCTORS
元件分類： 數(shù)字傳輸電路
英文描述： SDH/SONET STM1/OC3 postamplifier
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, UUC29
封裝： 1.55 X 1.55 MM, DIE-29
文件頁數(shù)： 6/28頁
文件大?。?/td> 143K
代理商： TZA3034U
1999 Nov 03
6
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 postamplifier
TZA3034
The relationship between the threshold current and the
detected input voltage is approximately:
(1)
In the formulas (1) and (3), the voltage on pin DIN and
pin DINQ is measured as peak-to-peak value.
Since the voltage on pin RSET is held constant at 1.5 V
below V
CCA
, the current flowing into this pin will be:
(2)
Combining these two formulas results in a general formula
to calculate R
ADJ
for a given input signal level detection:
(3)
Example:
Detection should occur if the differential voltage
of the input signals drops below 4 mV (p-p). In this case, a
reference current of 0.0018
×
0.004 = 7.2
μ
A should flow
into pin RSET. This can be set using a current source or
simply by connecting a resistor of the appropriate value.
The resistor must be connected between V
CCA
and
pin RSET. In this example the value would be:
The hysteresis is fixed internally at 3 dB electrical. In the
example of above, a differential level below 4 mV (p-p) of
the input signal will drive pin ST to LOW, and an input
signal level above 5.7 mV (p-p) will drive pin ST to HIGH.
A function is provided to automatically disable the signal
transmission when the chip senses that the input signal is
below the programmed threshold level. This function can
be put into operation by connecting pin JAM with pin STQ.
When the input signal is below the programmed threshold
level, the data outputs are then forced to a predetermined
state (pin DOUT = LOW and pin DOUTQ = HIGH).
Response time of the input signal level detection circuit is
determined by the time constant of the input capacitors,
together with the filter time constant (1
μ
s internal plus the
additional capacitor at pin CF). For SDH/SONET
applications, couple capacitors of 1.5 nF are
recommended, leading to a high-pass frequency of
approximately 30 kHz and a maximum assert time of
30
μ
s.
I
RSET
0.0018
V
DIN
V
DINQ
–
(
)
A
[ ]
×
=
I
RSET
R
ADJ
-1.5
[ ]
=
R
ADJ
DIN
V
DINQ
)
-V
[
]
=
R
ADJ
0.004
207.5 k
=
=
Dissipation
Since the thermal resistance from junction to ambient
R
th(j-a)
of the TSSOP package is higher than the thermal
resistance of the SO package (see Chapter “Thermal
characteristics”), the dissipation should be considered
when using the TZA3034TT version.
The formula to calculate the worst case die temperature is:
(4)
where
T
j
= junction temperature
T
amb
= ambient temperature
R
th(j-a)
= thermal resistance from junction to ambient
P
max
= maximum power dissipation.
For the TZA3034T (SO package), the worst case die
temperatureT
j
= 85 + 115
×
0.3 = 119.5
°
Cwhichisbelow
the maximum operating temperature.
For the TZA3034TT (TSSOP package), the worst case die
temperature T
j
= 85 + 150
×
0.3 = 130
°
C which is higher
than the maximum operating temperature, and therefore
strongly discouraged. It is recommended to lower the
thermalresistancefromjunctiontoambient,e.g.bymeans
of a dedicated board layout.
However, if the ambient temperature is limited to 75
°
C or
the power supply is limited to 3.3
±
0.3 V, the junction
temperature will stay below the maximum value without
further precautions.
PECL output circuits
The output circuit of ST and STQ is given in Fig.7.
The output circuit of DOUT and DOUTQ is given in Fig.8.
Some PECL termination schemes are given in Fig.9.
T
j
T
amb
R
th j
a
–
(
)
P
×
max
+
=
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