<<CLASSIFICATION>>
<<NDA MESSAGE>>
38
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
2
6
7
MSB IN2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
MASTER LSB OUT
BIT 6 . . . 1
5
8
10
11
PORT DATA
(CPOL 0)
(CPOL 1)
PORT DATA
SS1
(OUTPUT)
3
10
11
4
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
2
9
SPSCK
=
Figure 14. SPI master mode timing (CPHA=1)
Table 15. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in .
2
tSPSCK
SPSCK period
4 x tBus
—
ns
tBus = 1/fBus
3
tLead
Enable lead time
1
—
tBus
—
4
tLag
Enable lag time
1
—
tBus
—
5
tWSPSCK
Clock (SPSCK) high or low time
tBus - 30
—
ns
—
6
tSU
Data setup time (inputs)
15
—
ns
—
7
tHI
Data hold time (inputs)
25
—
ns
—
8
ta
Slave access time
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
tv
Data valid (after SPSCK edge)
—
25
ns
—
11
tHO
Data hold time (outputs)
0
—
ns
—
12
tRI
Rise time input
—
tBus - 25
ns
—
tFI
Fall time input
13
tRO
Rise time output
—
25
ns
—
tFO
Fall time output
Peripheral operating requirements and behaviors
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
27