參數(shù)資料
型號: TVP5040CPFP
廠商: TEXAS INSTRUMENTS INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP80
封裝: POWER, PLASTIC, TQFP-80
文件頁數(shù): 57/109頁
文件大?。?/td> 568K
代理商: TVP5040CPFP
2–35
The parallel host interface B timing is shown in Figure 2–34. The cycle is initiated by the host when VC2-RD or
VC1-WR transitions low. The TVP5040 responds by pulling VC0-RDY low. The TVP5040 then sets VC0-RDY to high
impedance. A pullup resistor is required to indicate the data was received or that the requested data is present on
the bus. The host then completes the cycle by pulling the asserted signal, VC2-RD or VC1-WR high.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsu(3)
A[1:0], CS setup until WR or RD active
10
ns
th(3)
A[1:0], CS hold after WR or RD inactive
10
ns
td(5)
Delay RDY low after WR or RD active
28
ns
tsu(4)
D[7:0] setup until WR active
5
ns
th(4)
D[7:0] hold after WR inactive
10
ns
tw(1)
RDY inactive pulse width
10
ns
tw(2)
WR inactive until any command active
80
ns
tsu(5)
(Read cycle) D[7:0] setup until RDY active
0
ns
th(5)
(Read cycle) D[7:0] hold after RD inactive
0
ns
td(6)
Delay WR or RD inactive after RDY active
0
ns
tw(3)
WR, RD command pulse width
40
ns
tsu(3)
th(3)
td(5)
tw(1)
td(6)
tsu(4)
th(4)
tsu(5)
th(5)
A[1:0]
D[7:0]
WRITE
RDY (VC0)
CS (VC3)
WR (VC1)
RD (VC2)
D[7:0]
READ
Write Data
Read Data
tw(3)
tw(2)
Figure 2–34. Parallel Host Interface B Timing
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