參數(shù)資料
型號(hào)： TVP5040CPFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 52/109頁(yè)
文件大小： 568K
代理商： TVP5040CPFP
2–31
2.8.4.3 FIFO Status 0 Register
The FIFO status 0 register returns two bits which report status and six unused bits.
7
6
5
4
3
2
1
0
Undefined
DREQA
Undefined
VIRQ
DREQA: DMA request for FIFO A. This bit is the same as the teletext threshold bit (bit 1 of the interrupt status register
at VIP subaddress 1C0). See section 2.14 for the definition of this bit.
VIRQ: This bit returns the status of the INTREQ terminal. Reading this bit does not clear the terminal.
COMMAND PHASE
DATA PHASE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FIFO status 0 read
0
1
0
d
0/1
d
0/1
There is no address phase associated with reading the FIFO status 0 register.
2.8.4.4 FIFO Status 1 Register
The FIFO status 1 register returns the status of the FIFO DMA channels in TVP5040.
7
6
5
4
3
2
1
0
Undefined
PRESENT-D (0)
R/W-C (1)
PRESENT-C (1)
R/W-B (0)
PRESENT-B (1)
R/W-A (1)
PRESENT-A (1)
R/W: This bit is set to 1 if the FIFO is a read port.
PRESENT: This bit is set to 1 if the FIFO is present, otherwise it is set to 0.
COMMAND PHASE
DATA PHASE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
FIFO status 1 read
0
1
0
1
0
1
0
1
There is no address phase associated with reading the VBI FIFO 1 register. This register is read-only and is always
set to 0x37.
2.8.4.5 VBI FIFO (FIFO A)
The VBI FIFO stores sliced VBI data in the format described in section 2.9.1. Data may be read from the FIFO at the
average rate of 1 data byte per 3 cycles (1 data cycles, 2 wait cycles) when the VIPCLK is at maximum speed.
COMMAND PHASE
DATA PHASE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
VBI FIFO read
0
1
0
1
0
D
There is no address phase associated with reading the VBI FIFO. FIFO polling is implemented.
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