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參數資料
| 型號： | TVP5040CPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數： | 39/109頁 |
| 文件大?。?/td> | 568K |
| 代理商： | TVP5040CPFP |
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2–19
2.7.2
I2C Write Operation
The data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to TVP5040 by generating a start condition followed by TVP5040s I2C
address 101110X , the X in the TVP5040 address is 0 when VC3 terminal is tied low and is 1 when VC3 terminal is
tied high, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the
TVP5040, the master presents the subaddress of the register, or the first of a block of registers it wants to write,
followed by one or more bytes of data, MSB first. The TVP5040 acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition.
STEP 1
0
I2C Start (master)
S
STEP 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
0
X
0
STEP 3
9
I2C Acknowledge (slave)
A
STEP 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
addr
STEP 5
9
I2C Acknowledge (slave)
A
STEP 6
7
6
5
4
3
2
1
0
I2C Write data (master)
Data
STEP 7
9
I2C Acknowledge (slave)
A
STEP 8
0
I2C Stop (master)
P
Repeat steps 6 and 7 until all data has been written.
2.7.3
I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates
a write operation to the TVP5040 by generating a start condition followed by the TVP5040s I2C address 101110X,
in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledge from the TVP5040, the
master presents the subaddress of the register, or the first of a block of registers it wants to read. After the cycle is
acknowledged, the master terminates the cycle immediately by generating a stop condition. The second phase is the
data phase. In this phase, a I2C master initiates a read operation to TVP5040 by generating a start condition followed
by the TVP5040s I2C address 101110X, in MSB first bit order, followed by a 1 to indicate a read cycle. After an
acknowledge from TVP5040, the I2C master receives one or more bytes of data from the TVP5040. The I2C master
acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the
TVP5040 to the master, the master generates a not acknowledge followed by a stop.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP5040CPFPG4 | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040EVM | 制造商:Texas Instruments 功能描述:EVAL BD TVP5040EVM USER S GUIDE - Bulk |
| TVP5145 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection |
| TVP5145EVM | 制造商:Texas Instruments 功能描述:TVP5145EVM - Bulk |
| TVP5145PFP | 功能描述:視頻 IC NTSC/PAL/SECAM/ Comp Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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