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參數資料
| 型號： | TVP3409-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Advanced Video Interface PALETTE(雙PLL，視頻接口調色器真彩色CMOS) |
| 中文描述： | 先進的視頻接口盒（雙鎖相環(huán)，視頻接口調色器真彩色的CMOS） |
| 文件頁數： | 29/57頁 |
| 文件大?。?/td> | 312K |
| 代理商： | TVP3409-135 |
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2–17
0
1
2
3
4
5
6
7
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
8
9
10
11
12
13
14
15
G0
G1
G2
G3
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
1
2
3
4
PCLK
Pixel Data
Inputs
Pixel
Outputs
R0
R1
R2
R3
R4
R5
R6
R7
B3
B4
B5
B6
B7
G3
G4
G5
R0
R1
R2
R3
R4
R5
R6
R7
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
G4
G5
G6
G7
G0
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
R0
R1
R2
R3
R4
R5
R6
R7
NOTE A: In this mode two pixels are delivered for every three pixel clocks. The internal clock multiplier factor is 2/3. Thus,
a 110-MHz PCLK results in a pixel rate of 73 Mpixels per second.
Figure 2–3. Mode 14, 24 Bits/Pixel, Packed in 16-Terminal Port Operation
2.6.4
The TVP3409 includes dual programmable clock synthesizers (PLLA, PLLB). The synthesizer signals are
output on the OTCLKA and OTCLKB terminals. An internal loop filter eliminates the need for external loop
filter components. The clock synthesizers are included to reduce the number of components on the circuit
board. This also reduces the high frequency signals on the circuit board by generating them internally.
Clock Synthesizers
One synthesizer can generate a pixel clock, the other synthesizer can generate a system or memory clock.
The synthesizers reset to a predefined frequency. The reset frequencies for the PLL clocks are shown in
Table 2–19.
The synthesizers are programmed by writing to the clock synthesizer control and indexed clock
configuration registers. These registers are included in the indexed register map of the RAMDAC (see Table
2–4 and Table 2–5).
The synthesizer includes a crystal oscillator for connection to an external crystal using XIN and XOUT. XIN
can also connect to a standard 14.318 MHz system clock. The synthesizer generates any frequency up to
the maximum frequency supported by the device. The maximum frequency is achieved by programming
the M, N, and P values in the synthesizer loop. Once the digital integer values have been programmed in
the register sets (up to four), the clock synthesizer control register bits can switch between the predefined
frequencies.
Upon reset, the M, N, and P values are loaded to give the reset frequencies in Table 2–19. The reset
frequencies can be changed by reloading new values for M, N, and P.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調色器) |
| TVP3703-135 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調色器) |
| TVP3703FN | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP5020TQFP | NTSC/PAL VIDEO DECODER |
| TVP5031 | NTSC/PAL VIDEO DECODER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP3409-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-135FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3409-170CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3409-170FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3703 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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