參數(shù)資料
型號: TVP3025-135
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE(三PLL,視頻接口調(diào)色器)
中文描述: 視頻接口盒(三鎖相環(huán),視頻接口調(diào)色器)
文件頁數(shù): 91/99頁
文件大?。?/td> 663K
代理商: TVP3025-135
B–1
Appendix B
RCLK Frequency < VCLK Frequency
The VCLK, RCLK, and SCLK outputs generated by the TVP3025 VIP are free-running clocks. The
video-control signals (i.e., HSYNC, VSYNC, and BLANK) are normally generated from VCLK, and a fixed
relationship between video-control signals and VCLK can be expected. If the TVP3025 is programmed to
sample and latch the BLANK input on the falling edge of VCLK some precautions must be observed. After
being sampled, it then looks at the internal RCLK signal to determine when to enable or disable SCLK at
the output terminal. The decision is determined when the RCLK frequency is greater than or equal to the
VCLK frequency. However, when the RCLK frequency is less than the VCLK frequency, the appearance of
the SCLK waveform at the output terminal (when BLANK is sampled low on the falling edge of VCLK) can
vary (see Figures B–1 and B–2).
To avoid this variation in the SCLK output waveform, the RCLK and VCLK frequencies should be chosen
so that HTOTAL is evenly divisible by the ratio of the VCLK frequency to the RCLK frequency:
remainder of [ HTOTAL/(VCLK frequency/RCLK frequency)] = 0
For example, if HTOTAL is even, VCLK frequency = DOTCLK frequency/8 and RCLK frequency = DOTCLK
frequency/16. Then the above formula is satisfied. NOTE: When HTOTAL starts at zero, then the formula
becomes:
remainder of [ (HTOTAL + 1)/(VCLK frequency/SCLK frequency) ] = 0.
VCLK
SYSBL
At Input
Terminal
RCLK
SCLK
Figure B–1. VCLK and SCLK Phase Relationship (Case 1)
VCLK
SYSBL
At Input
Terminal
RCLK
SCLK
Figure B–2. VCLK and SCLK Phase Relationship (Case 2)
相關(guān)PDF資料
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TVP3025-175 Video Interface PALETTE(三PLL,視頻接口調(diào)色器)
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