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參數(shù)資料
| 型號： | TVP3025-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 7/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-135 |
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1 Introduction
The TVP3025 is an advanced video interface palette (VIP) from Texas Instruments implemented in EPIC
0.8-micron CMOS process. The TVP3025 is a superset of the 64-bit TVP3020 VIP with the addition of
Brooktree BT485 register map emulation and frequency synthesis phase locked loops (PLLs). The BT485
register emulation mode allows the device to be software compatible with many graphics controllers,
including the S3 Vision964
and 86C928 VRAM based graphics accelerators. This new 64-bit device
provides an effective migration path from lower performance graphics systems which utilize previous
generation 32-bit color palettes.
The TVP3025 is a functional superset of the TVP3020 and features the same 64-bit programmable pixel
bus interface. Data can be split into 1, 2, 4, or 8 bit planes for pseudo-color mode or split into 12-, 16- or 24-bit
true-color and direct-color modes. For the 24-bit direct color modes, an 8-bit overlay plane is available. The
16-bit direct- and true-color modes can be configured to IBM XGA
(5, 6, 5), TARGA
(5, 5, 5, 1), or (6, 6,
4) as another existing format. An additional 12-bit mode (4, 4, 4, 4) is supported with 4 bits for each color
and overlay. All color modes support selection of little or big endian data format for the pixel bus. Additionally,
the device is also software compatible with the IMSG176/8 and Bt476/8 color palettes.
Clocking is provided through one of four inputs (2 TTL- and 1 ECL/TTL-compatible) or two crystal oscillator
inputs, and is software selectable. The video, shift clock, and reference clock outputs provide a
software-selected divide ratio of the chosen clock input. Two fully programmable PLLs for pixel clock and
memory clock functions are provided, as well as a simple frequency doubler for dramatic improvements in
graphics system cost and integration. A third loop clock PLL is incorporated making pixel data latch timing
much simpler than with other existing color palettes.
Like the TVP3020, the TVP3025 also integrates a complete, IBM XGA-compatible hardware cursor on chip,
making significant graphics performance enhancements possible. Additionally, auxiliary windowing,
port-select and color-keyed switching functions are provided, giving the user several efficient means of
producing graphical overlays on direct-color backgrounds.
The TVP3025 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters
(DACs) capable of directly driving a doubly terminated 75-
line. The lookup tables are designed with a
dual-ported RAM architecture that enables ultra-high speed operation. Sync generation is incorporated on
the green output channel. Horizontal sync and vertical sync are fed through the device and optionally
inverted to indicate screen resolution to the monitor. A palette-page register is available to provide the
additional bits of palette address when 1, 2, or 4 bit planes are used. This allows the screen colors to be
changed with only one microprocessor interface unit (MPU) write cycle.
The device features a separate VGA bus that allows data from the feature connector of most VGA-supported
personal computers to be fed directly into the palette without the need for external data multiplexing. The
separate bus also is useful in graphics accelerator applications, allowing effecient VGA and text mode
support.
The TVP3025 is highly system integrated. It can be connected to the serial port of VRAM devices without
external buffer logic and connected to many graphics engines directly. It also supports the split shift-register
transfer function, which is common to many industry standard VRAM devices.
The system-integration concept is carried to manufacturing test and field diagnosis. To support these,
several highly integrated test functions have been designed to enable simplified testing of the palette and
the entire graphics system.
EPIC is a trademark of Texas Instruments Incorporated.
XGA is a registered trademark of IBM.
TARGA is a registered trademark of Truevision Incorporated.
Vision964 is a trademark of S3 Corporation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-135PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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