參數(shù)資料
型號(hào): TTSI4K32T
廠商: Lineage Power
英文描述: 4096-Channel, 32-Highway Time-Slot Interchanger(4096通道、32路干線時(shí)隙交換機(jī))
中文描述: 4096通道,32道時(shí)隙交換器(4096通道,32路干線時(shí)隙交換機(jī))
文件頁數(shù): 30/64頁
文件大?。?/td> 1105K
代理商: TTSI4K32T
TTSI4K32T
4096-Channel, 32-Highway Time-Slot Interchanger
Data Sheet
June 2000
30
Lucent Technologies Inc.
JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:
1. Testing the connections between ICs on a particular board.
2. Observation of signals to the IC pins during normal operating functions.
3. Controlling the built-in self-test (BIST) of an IC. TTSI4K32T does not support BS-BIST.
Designed according to the IEEE Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the
test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin
ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16-state TAP controller,
an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and IDCODE
register). The main component is the BS register that links all the chip pins to a shift register by means of special
logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the
TTSI4K32T (the mode multiplexer of the BS output cells may be shared). Figure 14 illustrates the block diagram of
the TTSI4K32T’s BS test logic.
5-3923(F)r.4
Figure 14. Block Diagram of the TTSI4K32T's Boundary-Scan Test Logic
BOUNDARY-SCAN REGISTER
TDI
TRST
TMS
TCK
TAP
CONTROLLER
INSTRUCTION
DECODER
OUT
TDO
IN
MUX
CHIP KERNEL
(UNAFFECTED BY BOUNDARY-SCAN TEST)
IDCODE REGISTER
BYPASS REGISTER
INSTRUCTION REGISTER
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TTSI4K32T3BAL 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger
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