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參數(shù)資料
| 型號： | TTSI2K32T3BAL |
| 英文描述： | 2048-Channel, 32-Highway Time-Slot Interchanger |
| 中文描述： | 2048通道，32道時隙交換器 |
| 文件頁數(shù)： | 33/66頁 |
| 文件大?。?/td> | 1321K |
| 代理商： | TTSI2K32T3BAL |
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Preliminary Data Sheet
February 1999
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
33
Lucent Technologies Inc.
JTAG Boundary-Scan Specification
(continued)
Test Access Port Controller
(continued)
Table 11. TAP Controller States in the Data Register Branch
Table 12. TAP Controller States in the Instruction Register Branch
Name
Description
TEST LOGIC RESET
The BS logic is switched in such a way that normal operation of the ASIC is
adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET.
Irrespective of the initial state, the TAP controller has achieved TEST LOGIC
RESET after five control pulses at the latest when TMS = 1. The TAP controller
then remains in this state. This state is also achieved when TRST = 0.
Using the appropriate instructions, this state can activate circuit parts or initiate
a test. All of the registers remain in their present state if other instructions are
used.
This state is used for branching to the test data register control.
The test data is loaded in the test data register parallel to the rising edge of TCK
in this state.
The test data is clocked by the test data register serially to the rising edge of TCK
in the state. The TDO output driver is active.
This temporary state causes a branch to a subsequent state.
The input and output of test data can be interrupted in this state.
The test data is clocked into the second stage of the test data register parallel to
the falling edge of TCK in this state.
RUN TEST/IDLE
SELECT DR
CAPTURE DR
SHIFT DR
EXIT (1/2) DR
PAUSE DR
UPDATE DR
Name
SELECT IR
CAPTURE IR
Description
This state is used for branching to the instruction register control.
The instruction code 0001 is loaded in the first stage of the instruction register
parallel to the rising edge of TCK in this state.
The instructions are clocked into the instruction register serially to the rising edge
of TCK in the state. The TDO output driver is active.
This temporary state causes a branch to a subsequent state.
The input and output of instructions can be interrupted in this state.
The instruction is clocked into the second stage of the instruction register parallel
to the falling edge of TCK in this state.
SHIFT IR
EXIT (1/2) IR
PAUSE IR
UPDATE IR
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TTSI4K32T | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSI4K32T3BAL | 制造商:AGERE 制造商全稱:AGERE 功能描述:4096-Channel, 32-Highway Time-Slot Interchanger |
| TTSL-1 | 功能描述:電線鑒定 THERM. TRANS. SELFLAM LABEL RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| TTSL10VC3-5 | 功能描述:電線鑒定 ThermTrans, Self-Lam Label, Vinyl, .50" RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| TTSL126VC3-1 | 功能描述:電線鑒定 1.0" X 7.44" THERMAL RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
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