參數(shù)資料
型號： TTSI2K32T3BAL
英文描述： 2048-Channel, 32-Highway Time-Slot Interchanger
中文描述： 2048通道，32道時隙交換器
文件頁數(shù)： 23/66頁
文件大小： 1321K
代理商： TTSI2K32T3BAL
Preliminary Data Sheet
February 1999
TTSI2K32T
2048-Channel, 32-Highway Time-Slot Interchanger
23
Lucent Technologies Inc.
TDM Highway Interface Timing
(continued)
TDM Highway Alignment at Zero Offset
The TDM highway interface logic is designed to make interconnection to the TTSI2K32T as simple as possible.
Consider the timing diagram shown in Figure 11 below. Assume the following configuration register settings:
I
FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register.
I
FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register.
I
The Tx and Rx highways are all set for zero bit and time-slot offset.
I
The input CK speed is equal to the highway data rate.
One can see that time slot 0 of a frame coincides with the sampling of an active FSYNC.
At that edge:
I
Bit 0 of time slot 0 is latched from the Rx highway with the coincident clock.
I
Bit 0 of time slot 0 is transmitted starting with the coincident clock.
5-6958(F)r.2
Figure 11. Synchronization to FSYNC
TDM Highway Offsets
An offset may be added to the sampling of Rx time slot 0, bit 0 or the transmission of Tx time slot 0, bit 0. This can
be done on any of the receive and/or transmit highways, totally independent from one another. This is done by set-
ting the time-slot offset number, bit offset number, and fractional bit offset number on a per-highway basis using the
receive and transmit highway configuration registers. To illustrate this point, consider the timing diagram shown in
Figure 12 on page 24. Assume the following configuration register programming:
I
The input CK speed is set to 8.192 MHz.
I
FSYNC is active-high, FSP (bit 2) is set to 1 in the general command register.
I
FSYNC is sampled by the rising edge of CK, FSSE (bit 1) is set to 1 in the general command register.
I
The RXD0 highway is set for 3/4-bit offset and a highway data rate of 4.096 Mbits/s.
I
The TXD0 highway is set for 1-bit offset and a highway data rate of 2.048 Mbits/s.
One can see that bit 0 of the receive time slot 0 is sampled 1 and 1/2 CK cycles after FSYNC is sampled active.
Since CK is set for 8.192 MHz and RXD0 is set for 4.096 Mbits/s, then 1 and 1/2 CK cycles equals 3/4 of a
4.096 Mbits/s bit period.
FSYNC SAMPLED ACTIVE
Rx TIME SLOT 0 BIT 0 SAMPLE POINT
Rx TIME SLOT 0, BIT 0
Rx TIME SLOT 0, BIT 0
Tx TIME SLOT 0, BIT 0
Tx TIME SLOT 0, BIT 1
FSYNC
CK
T
X
HIGHWAY
R
X
HIGHWAY
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