參數(shù)資料
型號: TTRN012G7
廠商: Lineage Power
英文描述: Clock Synthesizer, 16:1 Data Multiplexer(2.5 Gbits/s and 2.7 Gbits/s)(時鐘合成器,16:1數(shù)據(jù)多路復用器(2.5 G位/秒和2.7 G位/秒))
中文描述: 時鐘合成器,16:1數(shù)據(jù)復用器(2.5 Gb /秒和2.7 Gb /秒)(時鐘合成器,16:1數(shù)據(jù)多路復用器(2.5摹位/秒和2.7克位/秒))
文件頁數(shù): 5/22頁
文件大?。?/td> 394K
代理商: TTRN012G7
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
5
Lucent Technologies Inc.
Pin Information
(continued)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
Note:
In Table 1, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-
preted as 2.48832 Gbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,
2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
I = input, O = output. I
u
indicates an internal pull-up resistor on this pin.
Pin
14
15
27
26
17
18
23
Symbol
*
D2G5P
D2G5N
LBDP
LBDN
CK2G5P
CK2G5N
RREF1
Type
O
Level
CML
Name/Description
Data Output (2.5 Gbits/s NRZ).
2.5 Gbits/s differential data
output.
Loopback Data Output.
Additional 2.5 Gbits/s differential data
output for system loopback.
Clock Output (2.5 GHz).
2.5 GHz differential clock output.
O
CML
O
CML
I
Analog
Resistor Reference 1.
CML current bias reference resistor.
(See Table 15, page 18 for values.)
Resistor Reference 2.
CML bias reference resistor. Connect a
1.5 k
resistor to V
CCD
.
Enable CK2G5P/N Clock Output.
0 = CK2G5P/N buffer powered off
1 or no connection = CK2G5P/N buffer enabled
Enable LBDP/N Data Output (Active-Low).
0 = LBDP/N buffer enabled
1 or no connection = LBDP/N buffer powered off
Invert D2G5P/N Data Output (Active-Low).
0 = invert
1 or no connection = noninvert
22
RREF2
I
Analog
21
ENCK2G5
I
u
CMOS
30
ENLBDN
I
u
CMOS
11
INVDATN
I
u
CMOS
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