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參數(shù)資料
| 型號： | TSXPC603RVGB/Q14LC |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 72/83頁 |
| 文件大?。?/td> | 8336K |
| 代理商： | TSXPC603RVGB/Q14LC |
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84
7707F–AVR–11/10
AT90USB82/162
12. External Interrupts
The External Interrupts are triggered by the INT7:0 pin or any of the PCINT12..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT12..0 pins are configured as
outputs. This feature provides a way of generating a software interrupt.
The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Regis-
ter control which pins contribute to the pin change interrupts. The Pin change interrupt PCI1 will
trigger if any enabled PCINT12:8 pin toggles. PCMSK1 Register control which pins contribute to
the pin change interrupts. Pin change interrupts on PCINT12 ..0 are detected asynchronously.
This implies that these interrupts can be used for waking the part also from sleep modes other
than Idle mode.
The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0)
and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered,
the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising
edge interrupts on INT7:4 requires the presence of an I/O clock, described in “System Clock and
Clock Options” on page 25. Low level interrupts and the edge interrupt on INT3:0 are detected
asynchronously. This implies that these interrupts can be used for waking the part also from
sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
12.0.1
External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits
The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 12-1. Edges on INT3..INT0 are registered asynchro-
nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 12-2 will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter-
rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur.
Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the
EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be
cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the
interrupt is re-enabled.
Bit
7654
3
2
1
0
ISC31
ISC30
ISC21
ISC20
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R/WR/W
Initial Value
0000
0
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