參數(shù)資料
型號(hào): TSL3301-LF
廠商: TAOS Inc.
英文描述: 102 】 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER
中文描述: 102】1非線性光學(xué)傳感器陣列與模擬到數(shù)字轉(zhuǎn)換器
文件頁數(shù): 5/16頁
文件大小: 247K
代理商: TSL3301-LF
TSL3301LF
102
×
1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C
APRIL 2007
5
The
LUMENOLOGY
Company
Copyright 2007, TAOS Inc.
www.taosinc.com
Register address map
The TSL3301
LF contains seven registers as defined in Table 2. Data in these registers may be written to or
read from using the
REGWrite
and
REGRead
commands. Three registers control the gain of the
analog-to-digital converters (ADC). Three other registers allow the offset of the system to be adjusted. Together
the gain and offset registers are used to maximize the achievable dynamic range.
Table 2. Register Address Map
ADDRESS
0x00
0x01
0x02
0x03
0x04
0x05
0x1F
REGISTER DESCRIPTION
Left (pixels 0
33) offset
Left (pixels 0
33) gain
Center (pixels 34
67) offset
Center (pixels 34
67) gain
Right (pixels 68
101) offset
Right (pixels 68
101) gain
Mode
REGISTER WIDTH
8
5
8
5
8
5
8
The offset registers are 8-bit sign-magnitude values and the gain registers are 5-bit values. The programmed
offset correction is applied to the sampled energy, and then the gain is applied. (i.e., the gain will affect the offset
correction.) These registers allow the user to maximize the dynamic range achievable in the given system.
The last register is the mode register. Bits in this register select the sleep mode as well as options for multichip
arrays and production testing. Note that test and multichip options do not apply to the 8-pin packaged device.
Users should always write zeros into the production test and multichip control bits.
0
7
0x1F
6
5
4
3
2
1
P2
MODE
0
0
SLP
P1
P0
C1
C0
SLP = Sleep Mode:
1
places device into sleep mode
0
places device in normal operating mode
C1, C0 are Reserved (should be written
0
)
P2 to P0 are factory test bits (should be written
0
)
Figure 1. Mode Register Bit Assignments
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