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參數(shù)資料
| 型號(hào)： | TSL3301-LF |
| 廠商： | TAOS Inc. |
| 英文描述： | 102 】 1 LINEAR OPTICAL SENSOR ARRAY WITH ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 102】1非線性光學(xué)傳感器陣列與模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 247K |
| 代理商： | TSL3301-LF |
TSL3301LF
102
×
1 LINEAR OPTICAL SENSOR ARRAY
WITH ANALOG-TO-DIGITAL CONVERTER
TAOS0078C
APRIL 2007
11
The
LUMENOLOGY
Company
Copyright 2007, TAOS Inc.
www.taosinc.com
Light-to-Digital Transfer Characteristics at V
DD
= 5 V, T
J
= 25
°
C,
λ
p
= 660 nm, t
int
= 250
μ
s (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bits
A-to-D converter resolution
8
Full scale reference
Full-scale reference
Gain register = 00000b
Gain register = 11111b
3.6
1.24
nJ/cm
2
Full-scale reference temperature sensitivity
For converter only, does not include
photodiode characteristics
±
150
ppm/
°
C
Average dark level offset
Average dark-level offset
Gain register = 00000b
Gain register = 11111b
Offset register 00000000b
Offset register = 00000000b
0
7
30
LSB
20
5
Dark signal nonuniformity (DSNU)
Gain register = 00000b, see Note 1
Gain register = 11111b, see Note 1
Gain register = 00000b
Ee = 11.3
μ
W/cm
2
Gain register = 11111b
Ee = 3.77
μ
W/cm
2
Ee = 11.3
μ
W/cm
2
, See Notes 2 and 3
10
14
LSB
Average white level output
Offset register =
00000000b
160
200
240
LSB
200
Pixel-response non-uniformity (PRNU)
Programmable offset steps
±
8%
±
128
0.5
1.5
±
10%
Programmable offset step size
Gain register = 00000b
Gain register = 11111b
LSB
Dark-level change with temperature
Differential nonlinearity
Integral nonlinearity
0
°
C < T
J
< 70
°
C
2
LSB
LSB
LSB
±
0.5
±
1
0.5
1.5
Dark level noise
Gain register = 00000b
Gain register = 11111b
LSB
NOTES:
1. DSNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is not
illuminated.
2. PRNU does not include DSNU.
3. PRNU is the difference between the highest value pixel and the lowest value pixel of the device under test when the array is uniformly
illuminated at nominal white level (typical average output level = 200).
Timing Requirements over recommended operating range (unless otherwise noted) (Figure 2)
MIN
10
30
30
20
20
NOM
MAX
UNIT
MHz
ns
ns
ns
ns
f
max
t
w(CLKH)
t
w(CLKL)
t
su
t
h
Maximum clock frequency
Clock high pulse duration
Clock low pulse duration
Input setup time
Input hold time
Switching Characteristics over recommended operating range (unless otherwise noted) (Figure 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
10
20
10
MAX
UNIT
ns
ns
ns
pF
t
r
t
f
t
d
C
i
Rise time, output
Fall time, output
Delay from clock edge to data-out stable
Input pin capacitance
C 20 pF
= 20 pF
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