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參數(shù)資料
| 型號： | TSC2003IPWRQ1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16 |
| 封裝： | GREEN, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 25/28頁 |
| 文件大?。?/td> | 560K |
| 代理商： | TSC2003IPWRQ1 |
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SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
TIMING CHARACTERISTICS (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Standard mode
250
tSU; DAT
Data setup time
Fast mode
100
ns
High-speed mode
10
Standard mode
0
3.45
s
Fast mode
0
0.9
tHD; DAT
Data hold time
High-speed mode, Cb = 100 pF max
0
70
ns
High-speed mode, Cb = 400 pF max
0
150
Standard mode
1000
Fast mode
20 + 0.1Cb
300
trCL
Rise time of SCL signal
ns
High-speed mode, Cb = 100 pF max
10
80
High-speed mode, Cb = 400 pF max
20
160
Standard mode
1000
Fast mode
20 + 0.1Cb
300
Rise time of SCL signal after a repeated Start
trCL1
ns
condition and after an acknowledge bit
High-speed mode, Cb = 100 pF max
10
80
High-speed mode, Cb = 400 pF max
20
160
Standard mode
300
Fast mode
20 + 0.1Cb
300
tfCL
Fall time of SCL signal
ns
High-speed mode, Cb = 100 pF max
10
80
High-speed mode, Cb = 400 pF max
20
160
Standard mode
1000
Fast mode
20 + 0.1Cb
300
trDA
Rise time of SDA signal
ns
High-speed mode, Cb = 100 pF max
10
80
High-speed mode, Cb = 400 pF max
20
160
Standard mode
300
Fast mode
20 + 0.1Cb
300
tfDA
Fall time of SDA signal
ns
High-speed mode, Cb = 100 pF max
10
80
High-speed mode, Cb = 400 pF max
20
160
Standard mode
4
s
tSU; STO
Setup time for Stop condition
Fast mode
600
ns
High-speed mode
160
Standard mode
400
Fast mode
400
Cb
Capacitive load for SDA or SCL
pF
High-speed mode, SCL = 1.7 MHz
400
High-speed mode, SCL = 3..4 MHz
100
Fast mode
0
50
tSP
Pulse width of spike suppressed
ns
High-speed mode
0
10
Standard mode
Noise margin at the high level for each
VnH
Fast mode
0.2 × VDD
V
connected device (including hysteresis)
High-speed mode
Standard mode
Noise margin at the low level for each
VnL
Fast mode
0.1 × VDD
V
connected device (including hysteresis)
High-speed mode
6
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TSC2003-Q1
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