參數(shù)資料
型號: TSC2003IPWRQ1
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO16
封裝: GREEN, PLASTIC, TSSOP-16
文件頁數(shù): 15/28頁
文件大?。?/td> 560K
代理商: TSC2003IPWRQ1
I2C High-Speed Operation
D11
D10
D9
D8
D7
D6
D5
D4
A
D3
D0
N
P
S
0
1
X
Sr
1
0
1
0
A1
A0
W
A
C3
C2
C1
C0
PD1
PD0
M
X
A
Sr
1
0
1
0
A1
A0
R
A
SCLH is stretched LOW until A/D Converter is finished converting data.
N
D2
D1
0
F/S Mode
HS-Mode Enabled
A/D Converter Power-Down Mode
A/D Converter Powers Up and Begins Sampling
Fixed Address Part
Programmable
A/D Converter Stops Sampling and Begins Conversion Using Internal Clock
A/D Converter Goes Into Power-Down Mode After Finishing Conversion (If PD0 = 0)
Exit HS-Mode and Enter F/S Mode
16 Bits + Ack
S = Start
Sr = Repeated Start
P = Stop
= Master Controls Bus
= Slave Controls Bus
Data Format
Output
Code
0V
FS = Full-Scale Voltage = V
REF
(1)
1LSB = V
REF
(1)/4096
FS – 1LSB
11...111
11...110
11...101
00...010
00...001
00...000
1LSB
NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2
Input Voltage (2) (V)
SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com
The TSC2003 can operate with high-speed I2C masters. To do so, the simple resistor pullup on SCL must be
changed to the active pullup, as recommended in the I2C specification.
The I2C bus operates in standard or fast mode initially. Following a Start condition, the master sends the code
00001xxx, which the slave does not acknowledge. The bus now operates in high-speed mode and remains in
high-speed mode until a Stop condition occurs. Therefore, to maximize throughput, only repeated Starts should
be used to separate transactions.
Because the TSC2003 may not have completed a conversion before a read to the part can be requested, the
TSC2003 is capable of stretching the clock until the converted data is stored in its internal shift register. Once the
data is latched, the TSC2003 releases the clock line so that the master can receive the converted data. A
complete high-speed conversion cycle is shown in Figure 16.
Figure 16. High-Speed I2C Mode Conversion Cycle
The TSC2003 output data is in straight binary format, as shown in Figure 17. This shows the ideal output code
for the given input voltage, and does not include the effects of offset, gain, or noise.
Figure 17. Ideal Input Voltages and Output Codes
22
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s): TSC2003-Q1
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