- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385949 > TSB14AA1AI (Texas Instruments, Inc.) 3.3 V IEEE 1394-1995 BACKPLANE PHY PDF資料下載
參數(shù)資料
| 型號(hào)： | TSB14AA1AI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3 V IEEE 1394-1995 BACKPLANE PHY |
| 中文描述： | 3.3伏電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995底板PHY |
| 文件頁數(shù)： | 12/37頁 |
| 文件大?。?/td> | 257K |
| 代理商： | TSB14AA1AI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
2
–
2
2.3.1
Link/PHY Interface
Four operations may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data
receive. The LLC issues a link service request to read or write a PHY register, or to request that the PHY gain control
of the serial-bus to transmit a packet. (refer to Section 5).
2.3.2
Arbitration Control
Controls the arbitrating sequence that the TSB14AA1A uses to arbitrate the bus between competing nodes (refer to
Section 6).
2.3.3
Data Resync/Decode
During packet reception, the data information is received on RDATA and strobe information is received on RSTRB.
The received data and strobe information is decoded to recover the received clock signal and the serial data bits,
which are resynchronized to the local system clock. The serial data bits are split into two parallel streams and sent
to the associated LLC.
2.3.4
Data/Arb Encode
During packet transmit, data bits to be transmitted are received from the LLC on two parallel paths and are latched
internally (in the TSB14AA1A) in synchronization with the system clock. These bits are combined serially, encoded,
and transmitted as the outbound data-strobe information stream. During transmit, the encoded data information is
transmitted on TDATA, and the encoded strobe information is transmitted on TSTRB.
2.3.5
CFRs
The configuration registers (CFRs) control the operation of the TSB14AA1A. The register definitions are specified
in Section 3.
2.3.6
Clock Generation
Provides system clock signals used to control transmission of the outbound encoded strobe and data information,
synchronization of the LLC and PHY, and is used for resynchronization of the received data.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB14AA1AT | 3.3 V IEEE 1394-1995 BACKPLANE PHY |
| TSB21LV03BI | IEEE 1394-1995 Triple-Cable Transceiver/Arbiter(IEEE1394-1995 三電纜收發(fā)器/判優(yōu)器) |
| TSB42AA4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PDT | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AA4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14AA1AIPFB | 功能描述:1394 接口集成電路 IEEE139419953.3V1prt 50/100Mbps BkplnPHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1AIPFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1APFB | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1APFBG4 | 功能描述:1394 接口集成電路 3.3V 1-port 50/100 Mbps Backplane PHY RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14AA1AT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3.3 V IEEE 1394-1995 BACKPLANE PHY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。