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參數(shù)資料
| 型號： | TSB12LV32-EP |
| 英文描述： | IC APEX 20KE FPGA 100K 324-FBGA |
| 中文描述： | 軍事增強塑料電機及電子學(xué)工程師聯(lián)合會1394-1995和P1394a兼容通用鏈路層控制器 |
| 文件頁數(shù)： | 60/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV32-EP |
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5
–
4
5.1
The data mover has eight modes of operation. There are four modes for transmit and four modes for receive.
Data Mover Data Flow Diagram
Definitions
Data mover port configured to operate in transmit mode means that the packet data is received
through the data mover port and forwarded (unbuffered) to the link core transmit logic to be sent
to the physical layer device (Phy), which will, in turn,
transmit
the data onto the 1394 bus.
Data mover port configured to operate in receive mode means that the packet data is
received
by the link core receive logic from the 1394 bus through the Phy. The data is then routed by the
link core to the data mover port without any internal buffering.
5.1.1
In all the isochronous receive modes, the packet header information is always loaded into the header
registers. The packet header quadlet is loaded into the Header0 register at 38h and the packet trailer quadlet
is loaded into the trailer register at 48h.
Isochronous Receive
5.1.1.1
Isochronous Packet Receive Without Header and Trailer
Step 1:
Isochronous packet is received through the receiver logic of the link core
Step 2:
The packet header is stripped off from the packet and loaded into the header0 register at
38h.
Step 3:
Packet data (payload only) is routed directly to the DM port without any buffering.
Step 4:
Trailer quadlet is loaded into the trailer register at 48h
CFR REGISTER
Step 1
Data
Mover
Port
Header0 Register at 38h
Trailer Register at 48h
LINK CORE
Transmitter
Receiver
Step 2
Step 4
Step 3 (Packet Data)
Packet received from
1394 bus through the
Phy
Figure 5
–
5. Isochronous Receive Without Header and Trailer
5.1.1.2
Isochronous Packet Receive With Header and Trailer
Step 1:
Isochronous packet is received through the receiver block of the link core.
Step 2:
The header quadlet is both loaded into the header0 register at 38h and routed to the DM
port without any buffering.
Step 3:
Packet data (payload only) is sent directly through the DM port only.
Step 4:
Trailer quadlet is loaded into the trailer register at 48h. It is also forwarded to the DM port.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB12LV32I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394-1995 and P1394a Compliant General-Purpose Link-Layer Controller |
| TSB12LV32IPZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32IPZEP | 制造商:Texas Instruments 功能描述:1394 I-TEMP 1394 GENERAL-PURPOSE LINK LAYER CONTROLLER (GP2L - Rail/Tube |
| TSB12LV32IPZG4 | 功能描述:1394 接口集成電路 General Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB12LV32PZ | 功能描述:1394 接口集成電路 General-Purpose Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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