參數(shù)資料
型號(hào): TSB12LV32-EP
英文描述: IC APEX 20KE FPGA 100K 324-FBGA
中文描述: 軍事增強(qiáng)塑料電機(jī)及電子學(xué)工程師聯(lián)合會(huì)1394-1995和P1394a兼容通用鏈路層控制器
文件頁數(shù): 53/106頁
文件大?。?/td> 605K
代理商: TSB12LV32-EP
3
16
aa
Byte 3
(MSByte)
Little Endian Processor
Memory
dd
(MSByte)
Byte 0
TSB12LV32 CFR/Memory
bb
Byte 2
cc
Byte 1
cc
Byte 1
bb
Byte 2
dd
Byte 0
(LSByte)
aa
(LSByte)
Byte 3
Figure 3
17. Little-Endian Data Invariance Illustration Chart
aa
Byte 3
(MSByte)
Little Endian Processor
Memory
dd
(MSByte)
Byte 0
TSB12LV32 CFR/Memory
bb
Byte 2
cc
Byte 1
cc
Byte 1
bb
Byte 2
dd
Byte 0
(LSByte)
aa
(LSByte)
Byte 3
Figure 3
18. Little-Endian Address Invariance Illustration Chart
3.3.5.3
Figure 3
18 shows a little-endian address invariant system design example. In this case, the byte ordering
between both systems is preserved (i.e., byte address is preserved). For example, byte 3 in the little endian
processor memory is also byte 3 in the TSB12LV32 CFR space. As Figure 3
18 shows, the byte ordering
is automatically maintained by the TSB12LV32 when in the address-invariance mode by swapping the order
in which the incoming bytes on the microprocessor are written to the CFRs.
Address Invariant System Design
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