參數(shù)資料
型號(hào)： TSA5523M
廠商： NXP Semiconductors N.V.
英文描述： Fan Finger Guard
中文描述： 1.4千兆赫的I2C總線控制的多媒體合成器
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 182K
代理商： TSA5523M
1996 Dec 17
6
Philips Semiconductors
Product specification
1.4 GHz I
2
C-bus controlled multimedia
synthesizer
TSA5523M
FUNCTIONAL DESCRIPTION
The device is controlled via the two-wire I
2
C-bus.
For programming, there is one module address (7 bits)
and the R/W bit for selecting the read or the write mode.
Write mode: R/W = 0
(see Table 1)
After the address transmission (first byte), data bytes can
be sent to the device. Four data bytes are needed to fully
program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or Control Byte (CB). The meaning of the bits
in the data bytes is given in Table 1.
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = 0) or control and ports
data (first bit = 1) will follow. Until an I
2
C-bus STOP
condition is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
The frequency register is loaded after the 8th clock pulse
of the second Divider Byte (DB2), the control register is
loaded after the 8th clock pulse of the control byte and the
ports register is loaded after the 8th clock pulse of the
Ports Byte (PB).
I
2
C-bus address selection
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 4) in one system by applying a
specific voltage to the AS input. The relationship between
MA1 and MA0 and the input voltage on the AS input is
given in Table 2.
Table 1
I
2
C-bus data format
Note
1.
A = Acknowledge.
Table 2
Explanation to Table 1
DATA BYTES
MSB
LSB
ACK
A
(1)
A
(1)
A
(1)
A
(1)
A
(1)
Address Byte (ADR)
Divider Byte 1 (DB1)
Divider Byte 2 (DB2)
Control Byte (CB)
Ports Byte (PB)
1
0
1
0
0
0
MA1
N10
N2
RSA
P2
MA0
N9
N1
RSB
P1
0
N14
N6
CP
P6
N13
N5
T2
P5
N12
N4
T1
P4
N11
N3
T0
P3
N8
N0
OS
P0
N7
1
P7
SYMBOL
DESCRIPTION
MA1 and MA0
N14 to N0
CP
CP = 0
CP = 1
T2, T1 and T0
RSA and RSB
OS
OS = 0
OS = 1
P7 to P0
Pn = 0
Pn = 1
programmable address bits (see Table 3)
programmable divider bits N = N14
×
2
14
+ 2
13
+ ... + N1
×
2 + N0
charge-pump current
50
μ
A
250
μ
A
test bits; normal operation; T2 = 0, T1 = 0, T0 = 1 (see Table 4)
reference divider ratio select bits (see Table 5)
tuning amplifier control bit
normal operation; tuning voltage is ON
tuning voltage is OFF (high impedance), IDC output voltage is LOW
NPN open-collector control bits
output n is OFF
output n is ON
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TSA5523M/C1 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.4 GHz I2C-bus controlled multimedia synthesizer
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