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參數(shù)資料
| 型號： | TSA5059ATS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2700 MHz, PDSO16 |
| 封裝： | PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 118K |
| 代理商： | TSA5059ATS |
2000 Oct 24
10
Philips Semiconductors
Product specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5059A
XT/COMP frequency output
It is possible to output either the crystal or the comparison
frequency at pin XT/COMP to be used in the application.
For example, to drive a second PLL synthesizer saving a
quartz crystal. To output f
xtal
it is necessary to set bit XCE
to logic 1 and bit XCS to logic 0 or bit XCE to logic 0 and
bit XCS to logic 1 during a test mode, while to output f
comp
it is necessary to set both bits XCE and XCS to logic 1.
Iftheoutputsignalatthispinisnotuseditisrecommended
to disable it by setting both bits XCE and XCS to logic 0.
Table 10 shows how this pin is programmed. At power-on
the XT/COMP output is set with the f
xtal
signal selected.
Prescaler enable
The TSA5059A is able to work with the relation
f
comp
= step size for an input frequency up to 2.3 GHz,
covering the complete satellite zero-IF frequency range.
For applications with an input frequency higher than
2.3 GHz it is necessary to use the prescaler by 2.
The prescaler is selected by setting bit PE to logic 1 and
it is not in use if bit PE is set to logic 0.
For satellite zero-IF applications (frequency between
950 and 2150 MHz), and especially if it is important to
reach a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0 and not to use the
prescaler allowing the comparison frequency to be equal
to the step size.
Test modes
It is possible to access the test modes by setting bit XCE
to logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0 as described in
Table 10.
Table 10
XT/COMP and test mode selection; note 1
Notes
1.
2.
X = don’t care.
Status at Power-on reset.
XCE
XCS
T2
T1
T0
XT/COMP OUTPUT
TEST MODE
0
1
1
0
0
0
1
1
X
X
X
0
X
X
X
0
X
X
X
0
disabled
f
xtal
f
comp
f
xtal
normal operation
normal operation
normal operation
test operation: charge pump sink;
status byte bit FL = 1
test operation: charge pump source;
status byte bit FL = 0
test operation: charge pump disabled;
status byte bit FL = 0
test operation:
1
2
f
DIV
switched to Port P0
test operation: drive output (pin DRIVE)
is off (low-voltage) to allow the tuning
voltage to reach the maximum value;
note 2
0
1
0
0
1
f
xtal
0
1
0
1
0
f
xtal
0
0
1
1
0
1
1
X
1
X
f
xtal
f
xtal
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| TSA5059TS | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5059 | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5059T | 2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSC2200 | PDA ANALOG INTERFACE CIRCUIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSA5059ATS/C1,118 | 功能描述:鎖相環(huán) - PLL 2,7GHZI2C BUS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TSA5059ATS/C2,118 | 制造商:NXP Semiconductors 功能描述: |
| TSA5059T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5059TS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2.7 GHz I2C-bus controlled low phase noise frequency synthesizer |
| TSA5060A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz I2C-bus controlled low phase noise frequency synthesizer |
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