參數(shù)資料
型號: TS88915T
英文描述: TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions
中文描述: TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時鐘驅(qū)動器。 3國70和100兆赫的版本
文件頁數(shù): 5/19頁
文件大小: 333K
代理商: TS88915T
5
TS88915T
2122A–HIREL–06/02
Absolute Maximum
Ratings
Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and affect
reliability.
Note:
Functional operating conditions are given in AC and DC electrical specifications.
Stresses beyond the absolute maximums listed may affect device reliability or cause per-
manent damage to the device.
Caution:
Input voltage must not be greater than the supply voltage by more than 2.5V at
all times including during power-on reset.
Mechanical and
Environment
The microcircuits shall meet all environmental requirements of either MIL-STD-883 for
class B devices or for Atmel standard screening.
Marking
The document that defines the markings is identified in the related reference docu-
ments. Each microcircuit is legible and permanently marked with the following
information as minimum:
Atmel Logo
Manufacturer’s Part Number
Class B Identification
Date-code of Inspection Lot
ESD Identifier If Available
Country of Manufacturing
Electrical
Characteristics
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the
relevant measurement conditions are given below:
Table Static Electrical Characteristics for the Electrical Variants
Table Dynamic Electrical Characteristics for TS88915T (70 MHz and 100 MHz
Versions)
Table 2.
Absolute Maximum Rating for the TS88915T
Parameter
Symbol
Min
Max
Unit
Supply Voltage
V
CC
-0.5
6.0
V
Input Voltage
V
in
-0.5
V
CC
+
0.5
V
Storage Temperature Range
T
stg
-65
+150
°
C
Power Dissipation
PGA Package
LDCC Package
P
D
500
mW
Thermal Resistance Junction-Case
PGA29
LDCC28
Θ
JC
-
-
7
7
°
C/W
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