參數(shù)資料
型號: TS88915T
英文描述: TS88915T [Updated 6/02. 19 Pages] Low Skew CMOS PLL Clock Driver. 3 state 70 and 100 MHZ versions
中文描述: TS88915T [更新6月2日。 19頁]低偏移的CMOS PLL時鐘驅動器。 3國70和100兆赫的版本
文件頁數(shù): 4/19頁
文件大小: 333K
代理商: TS88915T
4
TS88915T
2122A–HIREL–06/02
Signal Description
Scope
This drawing describes the specific requirements for the clock driver TS88915T, in com-
pliance with MIL-STD-883 class B or Atmel standard screening.
Applicable
Documents
1.
2.
MIL-STD-883: Test methods and procedures for electronics.
MIL-PRF-38535 appendix A: General specifications for microcircuits.
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2 and
Figure 3.
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-1835 (see “Package Mechan-
ical Data” on page 17).
Package
The macrocircuits are packaged in hermetically sealed ceramic packages, which con-
form to case outlines of MIL-STD-1835, but “Package Mechanical Data” on page 17.
The precise case outlines are described at the end of the specification (see “Package
Mechanical Data” on page 178) and into MIL-STD-1835.
Table 1.
Signal Index
Pin Name
Num
I/O
Signal Function
SYNC[0]
1
Input
Reference Clock Input
SYNC[1]
1
Input
Reference Clock Input
REF_SEL
1
Input
Chooses Reference Between SYNC[0] and SYNC[1]
FREQ_SEL
1
Input
Doubles VCO Internal Frequency
FEEDBACK
1
Input
Feedback Input to Phase Detector
RC1
1
Input
Input for External RC Network
Q(0-4)
5
Output
Clock Output (Locked to SYNC)
Q5
1
Output
Inverse of Clock Output
2x_Q
1
Output
2 x Clock Output (Q) Frequency (Synchronous)
Q/2
1
Output
Clock Output (Q) Frequency ÷ 2 (Synchronous)
LOCK
1
Output
Indicates Phase Lock has been Achieved (High when Locked)
OE/RST
1
Input
Output Enable/Asynchronous Reset (Active Low)
PLL_EN
1
Input
Disables Phase-lock for Low Frequency Testing
VCC, GND
11
Power
Power and Ground pins
Pins 8 and 10 are “analog” supply pins for internal PLL only
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