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| 型號： | TS8882VF20 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 1703K |
| 代理商： | TS8882VF20 |
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TS68882
2119A
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12/01
Figure 16.
Typical Coprocessor Configuration
Bus Interface Unit
All communications between the TS 68020/TS 68030 and the TS 68882 occur via standard TS
68000 Family bus transfers. The TS 68882 is designed to operate on 8-, 16-, or 32-bit data
buses.
The TS 68882 contains a number of coprocessor interface registers (CIRs) which are
addresses in the same manner as memory by the main processor. The TS 68000 Family
coprocessor interface is implemented via a protocol of reading and writing to these registers
by the main processor. The TS 68020 and TS 68030 implements this general purpose copro-
cessor interface protocol in hardware and microcode.
When the TS 68020/TS 68030 detects a typical TS 68882 instruction, the MPU writes the
instruction to the memory-mapped command CIR, and reads the response CIR. In this
response, the BIU encodes requests for any additional action required of the MPU on behalf of
the TS 68882. For example, the response may request that the MPU fetch an operand from
the evaluated effective address and transfer the operand to the operated CIR. Once the MPU
fulfills the coprocessor request(s), it is free to fetch and execute subsequent instructions.
A key concern in a coprocessor interface that allows concurrent instruction execution is syn-
chronization during main processor and coprocessor communication. If a subsequent
instruction is written to the TS 68882 before the CCU has passed the operands for the previ-
ous instructions to the ECU, the response instructs the TS 68020/TS 68030 to wait. Thus, the
choice of concurrent or nonconcurrent instruction execution is determined on an instruction-
by-instruction basis by the coprocessor.
The only difference between a coprocessor bus transfer and any other bus transfer is that the
TS 68020/TS 68030 issues a function code to indicate the CPU address space during the
cycle (the function codes are generated by the TS 68000 Family processors to identify eight
separate address spaces). Thus, the memory-mapped coprocessor interface registers do not
infringe upon instruction or data address spaces. The TS 68020/TS 68030 places a coproces-
sor ID field from the coprocessor instruction onto three of the upper address lines during
coprocessor accesses. This ID, along with the CPU address space function code, is decoded
to select one of eight coprocessors in the system.
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