Preliminary Beta-Site
Specification
MAIN FEATURES
§ 8-bit resolution.
§ ADC gain adjust.
§ 1.5 GHz full power input bandwidth.
§ 1 Gsps (min) sampling rate.
§ SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc
@ FS = 1 Gsps, FIN = 20 MHz :
§ SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc
@ FS = 1 Gsps, FIN = 500 MHz :
§ SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc
@ FS = 1 Gsps, FIN = 1000 MHz (-3 dB FS)
§ 2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.
§ DNL = 0.4 LSB
INL = 0.7 LSB.
§ Low Bit Error Rate (10
-13 ) @ 1 Gsps
§ Very low input capacitance : 3 pF
§ 500 mVpp differential or single-ended analog inputs.
§ Differential or single-ended 50
ECL compatible clock inputs.
§ ECL or LVDS/HSTL output compatibility.
§ Data ready output with asynchronous reset.
§ Gray or Binary selectable output data ; NRZ output mode.
§ Power consumption :
3.6 W @ Tj = 70°C
3.8 W @ Tj =125°C
§ Dual power supply : ± 5 V
§ Radiation tolerance oriented design (150 Krad (Si) measured).
APPLICATIONS
§ Digital Sampling Oscilloscopes.
§ Satellite receiver.
§ Electronic countermeasures / Electronic warfare.
§ Direct RF down–conversion.
SCREENING
§ Atmel-Grenoble standard screening level
§ Mil-PRF-38535, QML level Q for package version, DSCC 5962-00504
§ Temperature range: up to -55°C < Tc ; Tj < +125°C
DESCRIPTION
The TS8388BF is a monolithic 8–bit analog–to–digital converter, designed for
digitizing wide bandwidth analog signals at very high sampling rates of up to 1
Gsps.
The TS8388BF is using an innovative architecture, including an on chip Sample
and Hold (S/H), and is fabricated with an advanced high speed bipolar process
(B6HF from Siemens).
The on–chip S/H has a 2 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
F Suffix : CQFP 68
Ceramic Quad Flat Pack
ADC 8-bit 1 Gsps
TS8388BF
1/ Die form : JTS8388B
2/ Evaluation board :
TSEV8388BF
3/ Demultiplexer :
TS81102G0 : companion device available
Novembre 2000