參數(shù)資料
型號(hào)： TS8388BMF
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 46/62頁(yè)
文件大?。?/td> 1267K
代理商： TS8388BMF
50
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
10.5.1.10
(DG) Differential Gain
The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full Scale peak to
peak amplitude. F
IN = 5 MHz (TBC).
10.5.1.11
(DP) Differential Phase
Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale peak to
peak amplitude. F
IN = 5 MHz (TBC).
10.5.1.12
(TA) Aperture Delay
Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing point), and the
time at which (V
IN, VINB) is sampled.
10.5.1.13
(JITTER) Aperture Uncertainty
Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of
the signal at the sampling point.
10.5.1.14
(TS) Settling Time
Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step function is
applied to the differential analog input.
10.5.1.15
(ORT) Overvoltage Recovery Time
Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input is reduced
to midscale.
10.5.1.16
(TOD) Digital Data Output Delay
Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to the next
point of change in the differential output data (zero crossing) with specified load.
10.5.1.17
(TD1) Time Delay from Data to Data Ready
Time delay from Data transition to Data ready.
10.5.1.18
(TD2) Time Delay from Data Ready to Data
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period.
10.5.1.19
(TC) Encoding Clock Period
TC1 = Minimum clock pulse width (high) TC = TC1 + TC2
TC2 = Minimum clock pulse width (low)
10.5.1.20
(TPD) Pipeline Delay
Number of clock cycles between the sampling edge of an input data and the associated output data
being made available, (not taking in account the TOD). For the TS8388B the TPD is 4 clock periods.
10.5.1.21
(TRDR) Data Ready Reset Delay
Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the
reset to digital zero transition of the Data Ready output signal (DR).
相關(guān)PDF資料
PDF描述
TS8388BCFS 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BCF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BVF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BMFB/Q 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
TS8388BMF 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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TS8388BMFS9NB3 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:ADC 8-bit 1 GSPS
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