參數(shù)資料
型號(hào)： TS8388BMF
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 12/62頁(yè)
文件大小： 1267K
代理商： TS8388BMF
2
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
4.
Functional Description
4.1
Block Diagram
The following figure shows the simplified block diagram.
Figure 4-1.
Simplified Block Diagram
4.2
Functional Description
The TS8388B is an 8-bit 1 Gsps ADC based on an advanced high-speed bipolar technology featuring a
cutoff frequency of 25 GHz.
The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an analog
encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering an error
correction circuitry and a resynchronization stage followed by 75
differential output buffers.
The TS8388B works in fully differential mode from analog inputs up to digital outputs.
The TS8388B features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388B.
The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysilicon resis-
tors, which allow enhanced radiation tolerance (no performance drift measured at 150 kRad total dose).
MASTER/SLAVE TRACK & HOLD AMPLIFIER
VIN, VINB
CLOCK
BUFFER
GAIN
GORB
DATA, DATAB OR, ORB
DRRB DR, DRB
CLK, CLKB
4
5
4
5
8
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
INTERPOLATION
STAGES
REGENERATION
LATCHES
ERROR CORRECTION &
DECODE LOGIC
OUTPUT LATCHES &
BUFFERS
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