參數(shù)資料
型號: TS8388BCGL
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CBGA68
封裝: 1.27 MM PITCH, CERAMIC, BGA-68
文件頁數(shù): 61/62頁
文件大?。?/td> 1267K
代理商: TS8388BCGL
8
0860E–BDC–05/07
TS8388B
e2v semiconductors SAS 2007
Notes:
1. Differential output buffers are internally loaded by 75
resistors. Buffer bias current = 11 mA.
Total Harmonic Distortion
THD
–––
FS = 1 Gsps, FIN = 20 MHz
4
50
54
dB
F
S = 1 Gsps, FIN = 500 MHz
4
46
50
dB
FS = 1 Gsps, FIN = 1000 MHz (–1 dBFs)
4
42
46
dB
FS = 50 Msps, FIN = 25 MHz
1, 2, 6
46
45
dB
Spurious Free Dynamic Range
SFDR
–––
FS = 1 Gsps, FIN = 20 MHz
4
52
57
dBc
FS = 1 Gsps, FIN = 500 MHz
4
47
52
dBc
F
S = 1 Gsps, FIN = 1000 MHz (–1 dBFs)
4
42
47
dBc
FS = 1 Gsps, FIN = 1000 MHz (–3 dBFs)
4
45
50
dBc
FS = 50 Msps, FIN = 25 MHz
1, 2, 6
40
54
dBc
Two-tone Intermodulation Distortion
IMD
4
–––
FIN1 = 489 MHz at FS = 1 Gsps
F
IN2 = 490 MHz at FS = 1 Gsps
47
52
dBc
Switching Performance and Characteristics – See Figure 5-1 and Figure 5-2 on page 10
Maximum clock frequency
FS
–1
1.4
Gsps
Minimum clock frequency
F
S
4
10–50
Msps
Minimum Clock pulse width (high)
TC1
4
0.280
0.500
50
ns
Minimum Clock pulse width (low)
TC2
4
0.350
0.500
50
ns
Aperture delay
T
A
4
100
+250
400
ps
Aperture uncertainty
Jitter
4
0.4
0.6
ps (rms)
Data output delay
TDO
4
1150
1360
1660
ps
Output rise/fall time for DATA (20% to 80%)
TR/TF
4
250
350
550
ps
Output rise/fall time for DATA READY (20% to 80%)
TR/TF
4
250
350
550
ps
Data ready output delay
TDR
4
1110
1320
1620
ps
Data ready reset delay
TRDR
4
720
1000
ps
Data to data ready – Clock low pulse width
TOD-TDR
4
0
40
80
ps
Data to data ready output delay (50% duty cycle) at
TD1
4
420
460
500
ps
Data pipeline delay
TPD
4
clock
cycles
Table 5-3.
Electrical Specifications (Continued)
Parameter
Symbol
Test
Level
Value
Unit
Note
Min
Typ
Max
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