![](http://datasheet.mmic.net.cn/360000/TS8388BCG_datasheet_16675914/TS8388BCG_1.png)
Product Specification
MAIN FEATURES
8-bit resolution.
ADC gain adjust.
1.8 GHz full power input bandwidth.
1 Gsps (min) sampling rate.
SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc
@ F
S
= 1 Gsps, F
IN
= 20 MHz :
SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc
@ F
S
= 1 Gsps, F
IN
= 500 MHz :
SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc
@ F
S
= 1 Gsps, F
IN
= 1000 MHz (-3 dB FS)
2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.
DNL = 0.4 LSB
INL = 0.7 LSB.
Low Bit Error Rate (10
) @ 1 Gsps
Very low input capacitance : 3 pF
500 mVpp differential or single-ended analog inputs.
Differential or single-ended 50
ECL compatible clock inputs.
ECL or LVDS/HSTL output compatibility.
Data ready output with asynchronous reset.
Gray or Binary selectable output data ; NRZ output mode.
Power consumption :
3.9 W @ Tj = 70°C typical
APPLICATIONS
Digital Sampling Oscilloscopes.
Satellite receiver.
Electronic countermeasures / Electronic warfare.
Direct RF down–conversion.
Very High Speed Data Acquisition board
SCREENING
Atmel-Grenoble standard screening level
Temperature range: up to 0
°
C < Tc ; Tj < +90°C
DESCRIPTION
The TS8388BG is a monolithic 8–bit analog–to–digital converter, designed for
digitizing wide bandwidth analog signals at very high sampling rates of up to 1
Gsps.
The TS8388BG is using an innovative architecture, including an on chip Sample
and Hold (S/H), and is fabricated with an advanced high speed bipolar process
(B6HF from Siemens).
The on–chip S/H has a 1.8 GHz full power input bandwidth, providing excellent
dynamic performance in undersampling applications (High IF digitizing).
G Suffix : CBGA 72
Ceramic Ball Grid Array
With R and C decoupling on the package
ADC 8-bit 1 Gsps
TS8388BG
1/ Die form : JTS8388B
2/ Evaluation board :
TSEV8388BG
Detailed specification on request.
3/ Demultiplexer :
TS81102G0 : companion device available
January 2002