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參數(shù)資料
| 型號： | TS81102G0FS |
| 英文描述： | TS81102G0FS Summary [Updated 9/03. 10 Pages] DMUX 8/10 bit. 2 Gsps. 1:4/1:8. for military applications |
| 中文描述： | TS81102G0FS摘要[更新9 / 03。 10頁]分解器8 / 10位。 2 GSPS的。 1:4 / 1:8。軍事應(yīng)用 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 239K |
| 代理商： | TS81102G0FS |
3
TS81102G0FS
5344AS–BDC–09/03
Output Data
A[0…9]
B[0…9]
C[0…9]
D[0…9]
E[0…9]
F[0…9]
G[0…9]
H[0…9]
179, 180, 182, 183, 185, 186, 187, 188,
190, 191
56, 57, 59, 60, 62, 63, 65, 66, 67, 68
165, 166, 168, 169, 170, 171, 173, 174,
175, 176
71, 72, 74, 75, 76, 77, 79, 80, 81, 82
150, 151, 153, 154, 156, 157, 158, 159,
161, 162
85, 86, 88, 89, 90, 91, 93, 94, 96, 97
131, 132, 134, 135, 137, 138, 139, 140,
142, 143
104, 105, 107, 108, 110, 111, 113, 114,
116, 117
Output data
RefA to RefH
178, 55, 164, 70, 149, 84, 129, 103
Reference outputs (tied to the common
mode voltage of each port)
DR
125
In-phase Data Ready Signal (centered in
the output data, frequency = output data
frequency/2)
DRB
124
Inverted phase Data Ready Signal
(centered in the output data, frequency =
output data frequency /2)
TTL Input Signals
AsyncReset
192
Asynchronous reset (active high)
ClkInType
51
Input clock type:
DR mode = Logic 1
DR/2 mode = Logic 0
RatioSel
120
DMUX ratio selection:
1:4 mode = Logic 1
1:8 mode = Logic 0
NbBit
52
Number of bits selection
10 bits = Logic 1
8 bits = Logic 0
BIST
54
Built-in self-test mode (active low)
Other Output Signals
ADCDelAdjOUT
41
In-phase output of the stand-alone delay
cell
ADCDelAdjOUTB
42
Inverted phase output of the stand-alone
delay cell
Table 1.
Pin Description (Continued)
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